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dc.contributor.author
Greisen, Pierre
dc.contributor.author
Heinzle, Simon
dc.contributor.author
Gross, Markus
dc.contributor.author
Burg, Andreas P.
dc.date.accessioned
2019-09-09T10:05:45Z
dc.date.available
2017-06-09T18:28:41Z
dc.date.available
2019-09-09T10:05:45Z
dc.date.issued
2011
dc.identifier.issn
1687-5176
dc.identifier.issn
1687-5281
dc.identifier.other
10.1186/1687-5281-2011-18
en_US
dc.identifier.uri
http://hdl.handle.net/20.500.11850/44322
dc.identifier.doi
10.3929/ethz-b-000044322
dc.description.abstract
This paper presents a real-time processing platform for high-definition stereo video. The system is capable toprocess stereo video streams at resolutions up to 1, 920 × 1, 080 at 30 frames per second (1080p30). In the hybridFPGA-GPU-CPU system, a high-density FPGA is used not only to perform the low-level image processing tasks suchas color interpolation and cross-image color correction, but also to carry out radial undistortion, image rectification,and disparity estimation. We show how the corresponding algorithms can be implemented very efficiently inprogrammable hardware, relieving the GPU from the burden of these tasks. Our FPGA implementation results arecompared with corresponding GPU implementations and with other implementations reported in the literature.
en_US
dc.format
application/pdf
dc.language.iso
en
en_US
dc.publisher
Springer
en_US
dc.rights.uri
http://creativecommons.org/licenses/by/2.0/
dc.subject
Video processing pipeline
en_US
dc.subject
Stereoscopic video
en_US
dc.subject
FPGA
en_US
dc.subject
Disparity estimation
en_US
dc.subject
Image warping
en_US
dc.title
An FPGA-based processing pipeline for high-definition stereo video
en_US
dc.type
Journal Article
dc.rights.license
Creative Commons Attribution 2.0 Generic
ethz.journal.title
EURASIP Journal on Image and Video Processing
ethz.journal.volume
2011
en_US
ethz.journal.issue
1
en_US
ethz.journal.abbreviated
EURASIP J. Image Video Process.
ethz.pages.start
18
en_US
ethz.size
13 p.
en_US
ethz.version.deposit
publishedVersion
en_US
ethz.identifier.wos
ethz.identifier.nebis
006113997
ethz.publication.place
s.l.
en_US
ethz.publication.status
published
en_US
ethz.leitzahl
03228 - Fichtner, Wolfgang
en_US
ethz.leitzahl.certified
03228 - Fichtner, Wolfgang
ethz.date.deposited
2017-06-09T18:28:46Z
ethz.source
ECIT
ethz.identifier.importid
imp59364ed91a4bc96146
ethz.ecitpid
pub:73167
ethz.eth
yes
en_US
ethz.availability
Open access
en_US
ethz.rosetta.installDate
2017-07-19T11:10:27Z
ethz.rosetta.lastUpdated
2020-02-15T21:33:38Z
ethz.rosetta.versionExported
true
ethz.COinS
ctx_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.atitle=An%20FPGA-based%20processing%20pipeline%20for%20high-definition%20stereo%20video&rft.jtitle=EURASIP%20Journal%20on%20Image%20and%20Video%20Processing&rft.date=2011&rft.volume=2011&rft.issue=1&rft.spage=18&rft.issn=1687-5176&1687-5281&rft.au=Greisen,%20Pierre&Heinzle,%20Simon&Gross,%20Markus&Burg,%20Andreas%20P.&rft.genre=article&rft_id=info:doi/10.1186/1687-5281-2011-18&
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