VLSI Designs for Joint Channel Estimation and Data Detection in Large SIMO Wireless Systems

Open access
Date
2018-03Type
- Journal Article
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no
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Abstract
Channel estimation errors have a critical impact on the reliability of wireless communication systems. While virtually all existing wireless receivers separate channel estimation from data detection, it is well known that joint channel estimation and data detection (JED) significantly outperforms conventional methods at the cost of high computational complexity. In this paper, we propose a novel JED algorithm and corresponding VLSI designs for large single-input multiple-output (SIMO) wireless systems that use constant-modulus constellations. The proposed algorithm is referred to as PRojection Onto conveX hull (PrOX) and relies on biconvex relaxation (BCR), which enables us to efficiently compute an approximate solution of the maximum-likelihood JED problem. Since BCR solves a biconvex problem via alternating optimization, we provide a theoretical convergence analysis for PrOX. We design a scalable, high-throughput VLSI architecture that uses a linear array of processing elements to minimize hardware complexity. We develop corresponding field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) designs, and we demonstrate that PrOX significantly outperforms the only other existing JED design in terms of throughput, hardware-efficiency, and energy-efficiency. Show more
Permanent link
https://doi.org/10.3929/ethz-b-000448655Publication status
publishedExternal links
Journal / series
IEEE Transactions on Circuits and Systems I: Regular PapersVolume
Pages / Article No.
Publisher
IEEESubject
FPGA and ASIC designs; Joint channel estimation and data detection (JED); Large single-input multiple-output (SIMO) wireless systems; Biconvex relaxation (BCR)Organisational unit
09695 - Studer, Christoph / Studer, Christoph
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Is new version of: https://doi.org/10.3929/ethz-b-000448649
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