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dc.contributor.author
Wu, Michael
dc.contributor.author
Wang, Guohui
dc.contributor.author
Yin, Bei
dc.contributor.author
Studer, Christoph
dc.contributor.author
Cavallaro, Joseph R.
dc.contributor.editor
Matthews, Michael B.
dc.date.accessioned
2020-12-14T12:08:57Z
dc.date.available
2020-12-08T10:17:15Z
dc.date.available
2020-12-14T12:08:57Z
dc.date.issued
2013
dc.identifier.isbn
978-1-4799-2390-8
en_US
dc.identifier.isbn
978-1-4799-2388-5
en_US
dc.identifier.other
10.1109/ACSSC.2013.6810402
en_US
dc.identifier.uri
http://hdl.handle.net/20.500.11850/455233.1
dc.identifier.uri
http://hdl.handle.net/20.500.11850/455233
dc.identifier.doi
10.3929/ethz-b-000455233
dc.description.abstract
This paper compares two implementations of reconfigurable and high-throughput turbo decoders. The first implementation is optimized for an NVIDIA Kepler graphics processing unit (GPU), whereas the second implementation is for an Intel Ivy Bridge processor. Both implementations support max-log-MAP and log-MAP turbo decoding algorithms, various code rates, different interleaver types, and all block-lengths, as specified by HSPA; and LTE-Advanced. In order to ensure a fair comparison between both implementations, we perform device-specific optimizations to improve the decoding throughput and error-rate performance. Our results show that the Intel Ivy Bridge processor implementation achieves up to 2× higher decoding throughput than our GPU implementation. In addition our CPU implementation requires roughly 4× fewer codewords to be processed in parallel to achieve its peak throughput.
en_US
dc.format
application/pdf
en_US
dc.language.iso
en
en_US
dc.publisher
IEEE
en_US
dc.rights.uri
http://rightsstatements.org/page/InC-NC/1.0/
dc.title
HSPA+/LTE-A Turbo Decoder on GPU and Multicore CPU
en_US
dc.type
Conference Paper
dc.rights.license
In Copyright - Non-Commercial Use Permitted
ethz.book.title
2013 Asilomar Conference on Signals, Systems and Computers
en_US
ethz.pages.start
824
en_US
ethz.pages.end
828
en_US
ethz.size
5 p.
en_US
ethz.version.deposit
acceptedVersion
en_US
ethz.event
47th Asilomar Conference on Signals, Systems and Computers (Asilomar 2013)
en_US
ethz.event.location
Pacific Grove, CA, USA
en_US
ethz.event.date
November 3-6, 2013
en_US
ethz.publication.place
Piscataway, NJ
en_US
ethz.publication.status
published
en_US
ethz.leitzahl
ETH Zürich::00002 - ETH Zürich::00012 - Lehre und Forschung::00007 - Departemente::02140 - Dep. Inf.technologie und Elektrotechnik / Dep. of Inform.Technol. Electrical Eng.::02636 - Institut für Integrierte Systeme / Integrated Systems Laboratory::09695 - Studer, Christoph / Studer, Christoph
en_US
ethz.leitzahl.certified
ETH Zürich::00002 - ETH Zürich::00012 - Lehre und Forschung::00007 - Departemente::02140 - Dep. Inf.technologie und Elektrotechnik / Dep. of Inform.Technol. Electrical Eng.::02636 - Institut für Integrierte Systeme / Integrated Systems Laboratory::09695 - Studer, Christoph / Studer, Christoph
en_US
ethz.date.deposited
2020-12-08T10:17:26Z
ethz.source
FORM
ethz.eth
no
en_US
ethz.availability
Open access
en_US
ethz.rosetta.installDate
2021-02-15T22:11:42Z
ethz.rosetta.lastUpdated
2021-02-15T22:11:42Z
ethz.rosetta.versionExported
true
ethz.rosetta.versionExported
true
ethz.COinS
ctx_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.atitle=HSPA+/LTE-A%20Turbo%20Decoder%20on%20GPU%20and%20Multicore%20CPU&rft.date=2013&rft.spage=824&rft.epage=828&rft.au=Wu,%20Michael&Wang,%20Guohui&Yin,%20Bei&Studer,%20Christoph&Cavallaro,%20Joseph%20R.&rft.isbn=978-1-4799-2390-8&978-1-4799-2388-5&rft.genre=proceeding&rft_id=info:doi/10.1109/ACSSC.2013.6810402&rft.btitle=2013%20Asilomar%20Conference%20on%20Signals,%20Systems%20and%20Computers
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