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dc.contributor.author
Wu, Lianbo
dc.contributor.author
Burger, Thomas
dc.contributor.author
Schönle, Philipp
dc.contributor.author
Huang, Qiuting
dc.date.accessioned
2021-04-07T15:49:38Z
dc.date.available
2021-04-07T03:06:25Z
dc.date.available
2021-04-07T15:49:38Z
dc.date.issued
2021-04
dc.identifier.issn
0018-9200
dc.identifier.issn
1558-173X
dc.identifier.other
10.1109/JSSC.2020.3047431
en_US
dc.identifier.uri
http://hdl.handle.net/20.500.11850/477599
dc.description.abstract
This article presents a power-efficient low-jitter fractional-N digital phase-locked loop (DPLL) that resolves phase error (PE) in the fully differential voltage (FDV) domain. Compared with adopting a traditional time-to-digital converter (TDC), which relies on gate delay in the time domain, power-efficient quantization of PE by the proposed conversion scheme in the FDV domain can be accomplished with a higher power-supply/common-mode rejection ratio (PSRR/CMRR), lower process, voltage, and temperature (PVT) sensitivity, finer resolution, and better linearity. The implemented DPLL covers the fractional-N operation by a 10-bit differential current digital-to-analog converter (DAC) with a resistive load to represent the fractional phase/time. A differential dv/dt ramp is employed to linearly transfer the preset initial voltage into a small phase/voltage error, which is digitized by a narrow-range fine-resolution 7-bit self-timed successive-approximation-register analog-to-digital converter (SAR-ADC). The prototype DPLL, implemented in 130-nm CMOS, achieves 101-fs rms jitter, integrated from 10 kHz to 40 MHz, in the fractional-N mode with sub-12-bit fractional-frequency-control words, using an 80-MHz reference clock (REF), consuming 9.2 mW. This corresponds to a figure of merit (FoM) of -250.3 dB. The measured worst case fractional spur level is -56 dBc.
en_US
dc.language.iso
en
en_US
dc.publisher
IEEE
en_US
dc.subject
Analog-to-digital converter (ADC)
en_US
dc.subject
differential
en_US
dc.subject
digital controlled oscillator (DCO)
en_US
dc.subject
digital phase-locked loop (PLL)
en_US
dc.subject
fractional-N
en_US
dc.subject
frequency synthesizer
en_US
dc.subject
low jitter
en_US
dc.subject
ramp generation
en_US
dc.subject
sampling
en_US
dc.subject
time-to-digital converter (TDC)
en_US
dc.subject
voltage domain
en_US
dc.title
A Power-Efficient Fractional-N DPLL with Phase Error Quantized in Fully Differential-Voltage Domain
en_US
dc.type
Journal Article
dc.date.published
2021-01-12
ethz.journal.title
IEEE Journal of Solid-State Circuits
ethz.journal.volume
56
en_US
ethz.journal.issue
4
en_US
ethz.journal.abbreviated
IEEE j. solid-state circuits
ethz.pages.start
1254
en_US
ethz.pages.end
1264
en_US
ethz.identifier.scopus
ethz.publication.place
New York, NY
en_US
ethz.publication.status
published
en_US
ethz.date.deposited
2021-04-07T03:06:33Z
ethz.source
SCOPUS
ethz.eth
yes
en_US
ethz.availability
Metadata only
en_US
ethz.rosetta.installDate
2021-04-07T15:49:48Z
ethz.rosetta.lastUpdated
2021-04-07T15:49:48Z
ethz.rosetta.exportRequired
true
ethz.rosetta.versionExported
true
ethz.COinS
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