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dc.contributor.author
Chelini, Lorenzo
dc.contributor.author
Gysi, Tobias
dc.contributor.author
Grosser, Tobias
dc.contributor.author
Kong, Martin
dc.contributor.author
Corporaal, Henk
dc.date.accessioned
2021-06-16T16:43:55Z
dc.date.available
2021-06-16T02:56:18Z
dc.date.available
2021-06-16T16:43:55Z
dc.date.issued
2020-09
dc.identifier.isbn
978-1-4503-8075-1
en_US
dc.identifier.other
10.1145/3410463.3414635
en_US
dc.identifier.uri
http://hdl.handle.net/20.500.11850/489746
dc.description.abstract
To this day, polyhedral optimizing compilers use either extremely rigid (but accurate) cost models, one-size-fits-all general-purpose heuristics, or auto-tuning strategies to traverse and evaluate large optimization spaces. In this paper, we introduce an adaptive and automatic scheduler that permits to generate novel loop transformation sequences (or recipes) capable of delivering strong performance for a variety of different architectures without relying on auto-tuning, nor on pre-determined transformation strategies. We evaluate our approach using the Polybench/C benchmark suite against two modern state-of-the-art optimizers on three different architectures: An AMD ThreadRipper, an Intel Xeon Phi, and an Intel Xeon Platinum. Our results provide evidence that a set of high-level objectives backed up by an automatic adaptive scheduler (i.e., not hard-wired) is capable of achieving competitive performance, while only resorting to evaluating a handful of tuned variants.
en_US
dc.language.iso
en
en_US
dc.publisher
Association for Computing Machinery
dc.subject
affine transformations
en_US
dc.subject
polyhedral model
en_US
dc.subject
loop optimization
en_US
dc.title
Automatic generation of multi-objective polyhedral compiler transformations
en_US
dc.type
Conference Paper
dc.date.published
2020-09-30
ethz.book.title
PACT '20: Proceedings of the ACM International Conference on Parallel Architectures and Compilation Techniques
en_US
ethz.pages.start
83
en_US
ethz.pages.end
96
en_US
ethz.event
29th International Conference on Parallel Architectures and Compilation Techniques (PACT 2020)
en_US
ethz.event.location
Online
ethz.event.date
October 3-7, 2020
en_US
ethz.notes
Due to the Coronavirus (COVID-19) the conference was conducted virtually.
en_US
ethz.grant
Automatized compilation of sequential software to a diverse set of hardware accelerators
en_US
ethz.identifier.scopus
ethz.publication.place
New York, NY
ethz.publication.status
published
en_US
ethz.leitzahl
ETH Zürich::00002 - ETH Zürich::00012 - Lehre und Forschung::00007 - Departemente::02150 - Dep. Informatik / Dep. of Computer Science::02666 - Institut für Hochleistungsrechnersysteme / Inst. f. High Performance Computing Syst::03950 - Hoefler, Torsten / Hoefler, Torsten
ethz.leitzahl.certified
ETH Zürich::00002 - ETH Zürich::00012 - Lehre und Forschung::00007 - Departemente::02150 - Dep. Informatik / Dep. of Computer Science::02666 - Institut für Hochleistungsrechnersysteme / Inst. f. High Performance Computing Syst::03950 - Hoefler, Torsten / Hoefler, Torsten
ethz.grant.agreementno
168016
ethz.grant.fundername
SNF
ethz.grant.funderDoi
10.13039/501100001711
ethz.grant.program
Ambizione
ethz.date.deposited
2021-06-16T02:56:23Z
ethz.source
SCOPUS
ethz.eth
yes
en_US
ethz.availability
Metadata only
en_US
ethz.rosetta.installDate
2021-06-16T16:44:09Z
ethz.rosetta.lastUpdated
2024-02-02T14:07:52Z
ethz.rosetta.versionExported
true
ethz.COinS
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