A 13-b 1.1-MHz oversampled DAC with semidigital reconstruction filtering
dc.contributor.author
Francese, Pier A.
dc.contributor.author
Ferrat, Pascal
dc.contributor.author
Huang, Qiuting
dc.date.accessioned
2021-07-15T08:13:10Z
dc.date.available
2021-07-15T08:09:43Z
dc.date.available
2021-07-15T08:13:10Z
dc.date.issued
2004-12
dc.identifier.issn
0018-9200
dc.identifier.issn
1558-173X
dc.identifier.other
10.1109/JSSC.2004.836238
en_US
dc.identifier.uri
http://hdl.handle.net/20.500.11850/494695
dc.description.abstract
A digital-to-analog converter (DAC) composed of a cascaded digital /spl Sigma//spl Delta/ modulator and the combination of a semidigital/digital finite-impulse response (FIR) and an infinite-impulse response (IIR)-SC/RC filter is described. The architecture enables the analog linear reconstruction of 16/spl times/ oversampled digital signals. With the analog section implemented in CMOS 0.18-/spl mu/m and the digital part programmed into a field-programmable gate array (FPGA), the modulator plus reconstruction filter achieves a peak SNR of 78 dB. The spurious-free dynamic range reaches 80 dB and stays better than 73 dB within the 1.104-MHz signal band. A missing-tone-power ratio of 70 dB, demonstrated for a signal with 15-dB peak-to-average ratio, proves that the solution is suitable for ADSL-CO transmitters.
en_US
dc.language.iso
en
en_US
dc.publisher
IEEE
en_US
dc.subject
broadband transmitter
en_US
dc.subject
digital-analog conversion
en_US
dc.subject
reconstruction filter
en_US
dc.subject
semidigital finite-impulse response (FIR)
en_US
dc.subject
sigma-delta modulation
en_US
dc.subject
switched-capacitor (SC) filter
en_US
dc.subject
xDSL
en_US
dc.title
A 13-b 1.1-MHz oversampled DAC with semidigital reconstruction filtering
en_US
dc.type
Journal Article
dc.date.published
2004-11-30
ethz.journal.title
IEEE Journal of Solid-State Circuits
ethz.journal.volume
39
en_US
ethz.journal.issue
12
en_US
ethz.journal.abbreviated
IEEE J. Solid-State Circuits
ethz.pages.start
2098
en_US
ethz.pages.end
2106
en_US
ethz.identifier.wos
ethz.publication.place
New York, NY
en_US
ethz.publication.status
published
en_US
ethz.leitzahl
ETH Zürich::00002 - ETH Zürich::00012 - Lehre und Forschung::00007 - Departemente::02140 - Dep. Inf.technologie und Elektrotechnik / Dep. of Inform.Technol. Electrical Eng.::02636 - Institut für Integrierte Systeme / Integrated Systems Laboratory::03380 - Huang, Qiuting (emeritus) / Huang, Qiuting (emeritus)
en_US
ethz.leitzahl.certified
ETH Zürich::00002 - ETH Zürich::00012 - Lehre und Forschung::00007 - Departemente::02140 - Dep. Inf.technologie und Elektrotechnik / Dep. of Inform.Technol. Electrical Eng.::02636 - Institut für Integrierte Systeme / Integrated Systems Laboratory::03380 - Huang, Qiuting (emeritus) / Huang, Qiuting (emeritus)
ethz.relation.isNewVersionOf
20.500.11850/50568
ethz.date.deposited
2017-06-09T10:55:30Z
ethz.source
ECIT
ethz.identifier.importid
imp593652b0add3353683
ethz.identifier.importid
imp59364e0019d3780318
ethz.ecitpid
pub:148688
ethz.ecitpid
pub:55510
ethz.eth
yes
en_US
ethz.availability
Metadata only
en_US
ethz.rosetta.installDate
2021-07-15T08:09:52Z
ethz.rosetta.lastUpdated
2022-03-29T10:25:44Z
ethz.rosetta.versionExported
true
dc.identifier.olduri
http://hdl.handle.net/20.500.11850/164178
dc.identifier.olduri
http://hdl.handle.net/20.500.11850/34503
ethz.COinS
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Journal Article [133587]