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dc.contributor.author
Castañeda Fernández, Oscar
dc.contributor.author
Boynton, Zachariah
dc.contributor.author
Mirfarshbafan, Seyedhadi
dc.contributor.author
Huang, Shimin
dc.contributor.author
Ye, Jamie C.
dc.contributor.author
Molnar, Alyosha
dc.contributor.author
Studer, Christoph
dc.date.accessioned
2021-11-16T06:17:03Z
dc.date.available
2021-07-23T09:52:42Z
dc.date.available
2021-07-26T05:27:44Z
dc.date.available
2021-10-20T09:43:15Z
dc.date.available
2021-11-16T06:17:03Z
dc.date.issued
2021
dc.identifier.isbn
978-1-6654-3751-6
en_US
dc.identifier.isbn
978-1-6654-3752-3
en_US
dc.identifier.other
10.1109/ESSCIRC53450.2021.9567843
en_US
dc.identifier.uri
http://hdl.handle.net/20.500.11850/497324
dc.identifier.doi
10.3929/ethz-b-000497324
dc.description.abstract
All-digital millimeter-wave (mmWave) massive multi-user multiple-input multiple-output (MU-MIMO) receivers enable extreme data rates but require high power consumption. In order to reduce power consumption, this paper presents the first resolution-adaptive all-digital receiver ASIC that is able to adjust the resolution of the data-converters and baseband-processing engine to the instantaneous communication scenario. The scalable 32-antenna, 65 nm CMOS receiver occupies a total area of 8 mm^2 and integrates analog-to-digital converters (ADCs) with programmable gain and resolution, beamspace channel estimation, and a resolution-adaptive processing-in-memory spatial equalizer. With 6-bit ADC samples and a 4-bit spatial equalizer, our ASIC achieves a throughput of 9.98 Gb/s while being at least 2x more energy-efficient than state-of-the-art designs.
en_US
dc.format
application/pdf
en_US
dc.language.iso
en
en_US
dc.publisher
IEEE
en_US
dc.rights.uri
http://rightsstatements.org/page/InC-NC/1.0/
dc.title
A Resolution-Adaptive 8 mm2 9.98 Gb/s 39.7 pJ/b 32-Antenna All-Digital Spatial Equalizer for mmWave Massive MU-MIMO in 65nm CMOS
en_US
dc.type
Conference Paper
dc.rights.license
In Copyright - Non-Commercial Use Permitted
dc.date.published
2021-10-26
ethz.book.title
ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)
en_US
ethz.pages.start
247
en_US
ethz.pages.end
250
en_US
ethz.size
4 p. accepted version
en_US
ethz.version.deposit
acceptedVersion
en_US
ethz.event
47th European Solid State Circuits Conference (ESSCIRC 2021)
en_US
ethz.event.location
Online
en_US
ethz.event.date
September 13-22, 2021
en_US
ethz.identifier.scopus
ethz.publication.place
Piscataway, NJ
en_US
ethz.publication.status
published
en_US
ethz.leitzahl
ETH Zürich::00002 - ETH Zürich::00012 - Lehre und Forschung::00007 - Departemente::02140 - Dep. Inf.technologie und Elektrotechnik / Dep. of Inform.Technol. Electrical Eng.::02636 - Institut für Integrierte Systeme / Integrated Systems Laboratory::09695 - Studer, Christoph / Studer, Christoph
en_US
ethz.leitzahl.certified
ETH Zürich::00002 - ETH Zürich::00012 - Lehre und Forschung::00007 - Departemente::02140 - Dep. Inf.technologie und Elektrotechnik / Dep. of Inform.Technol. Electrical Eng.::02636 - Institut für Integrierte Systeme / Integrated Systems Laboratory::09695 - Studer, Christoph / Studer, Christoph
en_US
ethz.date.deposited
2021-07-23T09:52:46Z
ethz.source
FORM
ethz.eth
yes
en_US
ethz.availability
Open access
en_US
ethz.rosetta.installDate
2021-10-20T09:43:27Z
ethz.rosetta.lastUpdated
2021-10-20T09:43:27Z
ethz.rosetta.exportRequired
true
ethz.rosetta.versionExported
true
ethz.COinS
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