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dc.contributor.author
De Araujo Cavalcante, Matheus
dc.contributor.author
Riedel, Samuel
dc.contributor.author
Pullini, Antonio
dc.contributor.author
Benini, Luca
dc.date.accessioned
2021-08-05T07:20:42Z
dc.date.available
2021-08-05T03:10:43Z
dc.date.available
2021-08-05T07:20:42Z
dc.date.issued
2021-02
dc.identifier.isbn
978-3-9819263-5-4
en_US
dc.identifier.isbn
978-1-7281-6336-9
en_US
dc.identifier.other
10.23919/DATE51398.2021.9474087
en_US
dc.identifier.uri
http://hdl.handle.net/20.500.11850/499522
dc.description.abstract
A key challenge in scaling shared-L1 multi-core clusters towards many-core (more than 16 cores) configurations is to ensure low-latency and efficient access to the L1 memory. In this work we demonstrate that it is possible to scale up the shared-L1 architecture: We present MemPool, a 32 bit many-core system with 256 fast RV32IMA 'Snitch' cores featuring application-tunable execution units, running at 700 MHz in typical conditions (TT/0.80 V/25 °C). MemPool is easy to program, with all the cores sharing a global view of a large L1 scratchpad memory pool, accessible within at most 5 cycles. In MemPool's physical-aware design, we emphasized the exploration, design, and optimization of the low-latency processor-to-L1-memory interconnect. We compare three candidate topologies, analyzing them in terms of latency, throughput, and back-end feasibility. The chosen topology keeps the average latency at fewer than 6 cycles, even for a heavy injected load of 0.33 request/core/cycle. We also propose a lightweight addressing scheme that maps each core private data to a memory bank accessible within one cycle, which leads to performance gains of up to 20 % in real-world signal processing benchmarks. The addressing scheme is also highly efficient in terms of energy consumption since requests to local banks consume only half of the energy required to access remote banks. Our design achieves competitive performance with respect to an ideal, non-implementable full-crossbar baseline.
en_US
dc.language.iso
en
en_US
dc.publisher
IEEE
en_US
dc.subject
Many-core
en_US
dc.subject
MIMD
en_US
dc.subject
Networks-on-Chips
en_US
dc.title
MemPool: A Shared-L1 Memory Many-Core Cluster with a Low-Latency Interconnect
en_US
dc.type
Conference Paper
dc.date.published
2021-07-16
ethz.book.title
Proceedings of the 2021 Design, Automation & Test in Europe (DATE 2021)
en_US
ethz.pages.start
701
en_US
ethz.pages.end
706
en_US
ethz.event
24th Design, Automation and Test in Europe Conference (DATE 2021)
en_US
ethz.event.location
Online
en_US
ethz.event.date
February 1-5, 2021
en_US
ethz.identifier.scopus
ethz.publication.place
Piscataway, NJ
en_US
ethz.publication.status
published
en_US
ethz.leitzahl
ETH Zürich::00002 - ETH Zürich::00012 - Lehre und Forschung::00007 - Departemente::02140 - Dep. Inf.technologie und Elektrotechnik / Dep. of Inform.Technol. Electrical Eng.::02636 - Institut für Integrierte Systeme / Integrated Systems Laboratory::03996 - Benini, Luca / Benini, Luca
ethz.leitzahl.certified
ETH Zürich::00002 - ETH Zürich::00012 - Lehre und Forschung::00007 - Departemente::02140 - Dep. Inf.technologie und Elektrotechnik / Dep. of Inform.Technol. Electrical Eng.::02636 - Institut für Integrierte Systeme / Integrated Systems Laboratory::03996 - Benini, Luca / Benini, Luca
ethz.date.deposited
2021-08-05T03:10:54Z
ethz.source
SCOPUS
ethz.eth
yes
en_US
ethz.availability
Metadata only
en_US
ethz.rosetta.installDate
2021-08-05T07:20:50Z
ethz.rosetta.lastUpdated
2022-03-29T10:56:44Z
ethz.rosetta.versionExported
true
ethz.COinS
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