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dc.contributor.author
Büchel, Julian
dc.contributor.author
Kakon, Jonathan
dc.contributor.author
Perez, Michel
dc.contributor.author
Indiveri, Giacomo
dc.date.accessioned
2021-11-25T13:12:27Z
dc.date.available
2021-11-13T07:54:54Z
dc.date.available
2021-11-25T13:12:27Z
dc.date.issued
2021
dc.identifier.isbn
978-1-7281-9201-7
en_US
dc.identifier.other
10.1109/ISCAS51556.2021.9401767
en_US
dc.identifier.uri
http://hdl.handle.net/20.500.11850/515020
dc.description.abstract
Efficient Balanced Networks (EBNs) are networks of spiking neurons in which excitatory and inhibitory synaptic currents are balanced on a short timescale, leading to desirable coding properties such as high encoding precision, low firing rates, and distributed information representation. It is for these benefits that it would be desirable to implement such networks in low-power neuromorphic processors. However, the degree of device mismatch in analog mixed-signal neuromorphic circuits renders the use of pre-trained EBNs challenging, if not impossible. To overcome this issue, we developed a novel local learning rule suitable for on-chip implementation that drives a randomly connected network of spiking neurons into a tightly balanced regime. Here we present the integrated circuits that implement this rule and demonstrate their expected behaviour in low-level circuit simulations. Our proposed method paves the way towards a system-level implementation of tightly balanced networks on analog mixed-signal neuromorphic hardware. Thanks to their coding properties and sparse activity, neuromorphic electronic EBNs will be ideally suited for extreme-edge computing applications that require low-latency, ultra-low power consumption and which cannot rely on cloud computing for data processing. © 2021 IEEE
en_US
dc.language.iso
en
en_US
dc.publisher
IEEE
en_US
dc.subject
balanced networks
en_US
dc.subject
neuromorphic computing
en_US
dc.title
Implementing Efficient Balanced Networks with Mixed-Signal Spike-Based Learning Circuits
en_US
dc.type
Conference Paper
dc.date.published
2021-04-27
ethz.book.title
2021 IEEE International Symposium on Circuits and Systems (ISCAS)
en_US
ethz.pages.start
9401767
en_US
ethz.size
5 p.
en_US
ethz.event
IEEE International Symposium on Circuits and Systems (ISCAS 2021)
en_US
ethz.event.location
Daegu, South Korea
en_US
ethz.event.date
May 22-28, 2021
en_US
ethz.identifier.wos
ethz.publication.place
Piscataway, NJ
en_US
ethz.publication.status
published
en_US
ethz.leitzahl
ETH Zürich::00002 - ETH Zürich::00012 - Lehre und Forschung::00007 - Departemente::02140 - Dep. Inf.technologie und Elektrotechnik / Dep. of Inform.Technol. Electrical Eng.::02533 - Institut für Neuroinformatik / Institute of Neuroinformatics::09699 - Indiveri, Giacomo / Indiveri, Giacomo
ethz.leitzahl.certified
ETH Zürich::00002 - ETH Zürich::00012 - Lehre und Forschung::00007 - Departemente::02140 - Dep. Inf.technologie und Elektrotechnik / Dep. of Inform.Technol. Electrical Eng.::02533 - Institut für Neuroinformatik / Institute of Neuroinformatics::09699 - Indiveri, Giacomo / Indiveri, Giacomo
ethz.date.deposited
2021-11-13T07:56:53Z
ethz.source
WOS
ethz.eth
yes
en_US
ethz.availability
Metadata only
en_US
ethz.rosetta.installDate
2021-11-25T13:12:35Z
ethz.rosetta.lastUpdated
2022-03-29T16:09:03Z
ethz.rosetta.versionExported
true
ethz.COinS
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