Metadata only
Date
2021-12Type
- Journal Article
Abstract
Modern Internet of Things (IoT) end nodes must support computational intensive workloads at a limited power budget. Parallel ultra-low-power (PULP) architectures are a promising target for this scenario, and the availability of highly optimized software libraries is crucial to exploit parallelism and reduce software development costs. This letter proposes an efficient parallel design of the widely used short-time Fourier transform (STFT) and discrete wavelet transform (DWT) transforms targeting ultra-low-power IoT devices. We address key performance challenges related to fine-grained synchronization and banking conflicts in shared memory. We achieve high throughput (50.95 samples/ μs, on average), good parallel speedup (up to 6.79× ), and high energy efficiency (up to 172.55 GOp/s/W) on a cluster of eight RISC-V cores optimized for PULP operation. Show more
Publication status
publishedExternal links
Journal / series
IEEE Embedded Systems LettersVolume
Pages / Article No.
Publisher
IEEEOrganisational unit
03996 - Benini, Luca / Benini, Luca
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