Declarative Power Sequencing using a CPLD

Abstract

Declarative power sequencing solves the difficult and tedious problem of bringing up and managing the power resources of a computing platform by describing the platform in a declarative model and applying constraint solving to obtain correct power sequences from the model. To date these generated power sequences are wholly executed on the board management controller (BMC). However, some platforms provide specialized hardware for the purpose of power sequencing which goes unused. The Enzian research computer for instance features two power sequencing Complex Programmable Logic Devices (CPLDs) which the BMC remote controls when executing power sequences. The goal of this thesis is to devise an algorithm to partition a generated power sequence such that it can leverage the capabilities of specialized hardware and to generate instructions for the power sequencing CPLDs on Enzian.