A 330μW 1.25ps 400fs-INL vernier time-to-digital converter with 2D reconfigurable spiral arbiter array and 2nd-order ΔΣ linearization

Abstract

This work presents an 8-bit 1.25ps resolution Vernier TDC with 2D reconfigurable spiral arbiter array and ΔΣ linearization for ADPLL. The 2D spiral arbiter array improves both linearity and detection range. The quantization errors introduced by delay cells and 2D arbiter array folding points are minimized using a reconfigurable arbiter array with 2 nd order ΔΣ modulators. The prototype in a 45nm CMOS technology consumes 0.3mW power under a 1V power supply with 80MHz conversion rate. The measured maximum DNL/INL are 0.31/0.4 ps with ΔΣ linearization and 1.35/1.03 ps without ΔΣ linearization, respectively.