A D-band (110 to 170 GHz) SPDT switch in 32 nm CMOS SOI

Abstract

This work demonstrates the implementation of a D-band single-pole double-throw switch(SPDT) in 32 nm CMOS SOI technology. A tuned shunt topology is used to achieve the lowest insertion loss. The switch demonstrates state-of-the art performance showing an insertion loss of 2.6 dB at 140 GHz and good matching across the whole D-band. Measurements also show high isolation of greater than 20 dB from 110 to 170 GHz. This is the lowest insertion loss of an SPDT switch that has been designed for the D-band and reported in a 32 nm CMOS SOI process.