A broadband CMOS digital power amplifier with hybrid Class-G Doherty efficiency enhancement
dc.contributor.author
Hu, Song
dc.contributor.author
Kousai, Shouhei
dc.contributor.author
Wang, Hua
dc.date.accessioned
2022-06-03T09:31:16Z
dc.date.available
2022-06-02T13:16:30Z
dc.date.available
2022-06-03T09:31:16Z
dc.date.issued
2015
dc.identifier.isbn
978-1-4799-6224-2
en_US
dc.identifier.isbn
978-1-4799-6223-5
en_US
dc.identifier.issn
0193-6530
dc.identifier.issn
2376-8606
dc.identifier.other
10.1109/ISSCC.2015.7062917
en_US
dc.identifier.uri
http://hdl.handle.net/20.500.11850/550596
dc.description.abstract
Spectrum-efficient modulations in modern wireless systems often result in large peak-to-average power ratios (PAPRs) for the transmitted signals. Therefore, PA efficiency at deep power back-off (PBO) levels (e.g., -12dB) becomes critical to extend the mobile's battery life. Classic techniques, i.e., outphasing, envelope tracking, and Doherty PAs, offer marginal efficiency improvement at deep PBO in practice. Dual-mode PAs require switches at the PA output for high-/low-power mode selection [1,2], posing reliability and linearity challenges. Although simple supply switching (Class-G) is effective at deep PBO, it only offers Class-B-like PBO efficiency in each supply mode [3,4]. Multi-level outphasing PA requires multiple supplies and frequent supply switching [5], resulting in substantial DC-DC converter overhead and exacerbated switching noise.
en_US
dc.language.iso
en
en_US
dc.publisher
IEEE
en_US
dc.title
A broadband CMOS digital power amplifier with hybrid Class-G Doherty efficiency enhancement
en_US
dc.type
Other Conference Item
dc.date.published
2015-03-19
ethz.book.title
2015 IEEE International Solid-State Circuits Conference (ISSCC)
en_US
ethz.journal.title
Digest of Technical Papers / IEEE International Solid State Circuits Conference
ethz.journal.volume
58
en_US
ethz.journal.abbreviated
Dig. tech. pap.- IEEE Int. Solid-State Circuits Conf.
ethz.pages.start
44
en_US
ethz.pages.end
46
en_US
ethz.event
62nd IEEE International Solid-State Circuits Conference (ISSCC 2015)
en_US
ethz.event.location
San Francisco, CA, USA
en_US
ethz.event.date
February 22-26, 2015
en_US
ethz.publication.place
Piscataway, NJ
en_US
ethz.publication.status
published
en_US
ethz.leitzahl
ETH Zürich::00002 - ETH Zürich::00012 - Lehre und Forschung::00007 - Departemente::02140 - Dep. Inf.technologie und Elektrotechnik / Dep. of Inform.Technol. Electrical Eng.::02636 - Institut für Integrierte Systeme / Integrated Systems Laboratory::09757 - Wang, Hua / Wang, Hua
en_US
ethz.leitzahl.certified
ETH Zürich::00002 - ETH Zürich::00012 - Lehre und Forschung::00007 - Departemente::02140 - Dep. Inf.technologie und Elektrotechnik / Dep. of Inform.Technol. Electrical Eng.::02636 - Institut für Integrierte Systeme / Integrated Systems Laboratory::09757 - Wang, Hua / Wang, Hua
en_US
ethz.date.deposited
2022-06-02T13:16:35Z
ethz.source
BATCH
ethz.eth
no
en_US
ethz.availability
Metadata only
en_US
ethz.rosetta.installDate
2022-06-03T09:31:22Z
ethz.rosetta.lastUpdated
2024-02-02T17:22:35Z
ethz.rosetta.exportRequired
true
ethz.rosetta.versionExported
true
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