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dc.contributor.author
Renner, Alpha
dc.contributor.author
Sandamirskaya, Yulia
dc.contributor.author
Sommer, Friedrich
dc.contributor.author
Paxon Frady, Edward
dc.contributor.editor
Potok, Thomas E.
dc.contributor.editor
Schuman, Catherine
dc.date.accessioned
2022-10-10T06:08:16Z
dc.date.available
2022-10-01T03:23:25Z
dc.date.available
2022-10-10T06:08:16Z
dc.date.issued
2022-07
dc.identifier.isbn
978-1-4503-9789-6
en_US
dc.identifier.other
10.1145/3546790.3546820
en_US
dc.identifier.uri
http://hdl.handle.net/20.500.11850/573816
dc.description.abstract
Vector Symbolic Architectures (VSA) were first proposed as connectionist models for symbolic reasoning, leveraging parallel and in-memory computing in brains and neuromorphic hardware that enable low-power, low-latency applications. Symbols are defined in VSAs as points/vectors in a high-dimensional neural state-space. For spiking neuromorphic hardware (and brains), particularly sparse representations are of interest, as they minimize the number of costly spikes. Furthermore, sparse representations can be efficiently stored in simple Hebbian auto-associative memories, which provide error correction in VSAs. However, the binding of spatially sparse representations is computationally expensive because it is not local to corresponding pairs of neurons as in VSAs with dense vectors. Here, we present the first implementation of a sparse VSA on spiking neuromorphic hardware, specifically Intel's neuromorphic research chip Loihi. To reduce the cost of binding, a delay line and coincidence detection are used, trading off space with time. We show as proof of principle that our network on Loihi can perform the binding operation of a classical analogical reasoning task and discuss the cost of different sparse binding operations. The proposed binding mechanism can be used as a building block for VSA-based architectures on neuromorphic hardware.
en_US
dc.format
application/pdf
en_US
dc.language.iso
en
en_US
dc.publisher
Association for Computing Machinery
en_US
dc.title
Sparse Vector Binding on Spiking Neuromorphic Hardware Using Synaptic Delays
en_US
dc.type
Conference Paper
dc.date.published
2022-09-07
ethz.book.title
ICONS '22: Proceedings of the International Conference on Neuromorphic Systems 2022
en_US
ethz.pages.start
27
en_US
ethz.size
5 p.
en_US
ethz.event
ICONS: International Conference on Neuromorphic Systems Knoxville TN USA (ICONS 2022)
en_US
ethz.event.location
Knoxville, TN, USA
en_US
ethz.event.date
July 27-29, 2022
en_US
ethz.identifier.scopus
ethz.publication.place
New York, NY
en_US
ethz.publication.status
published
en_US
ethz.leitzahl
ETH Zürich::00002 - ETH Zürich::00012 - Lehre und Forschung::00007 - Departemente::02140 - Dep. Inf.technologie und Elektrotechnik / Dep. of Inform.Technol. Electrical Eng.::02533 - Institut für Neuroinformatik / Institute of Neuroinformatics::09699 - Indiveri, Giacomo / Indiveri, Giacomo
ethz.leitzahl.certified
ETH Zürich::00002 - ETH Zürich::00012 - Lehre und Forschung::00007 - Departemente::02140 - Dep. Inf.technologie und Elektrotechnik / Dep. of Inform.Technol. Electrical Eng.::02533 - Institut für Neuroinformatik / Institute of Neuroinformatics::09699 - Indiveri, Giacomo / Indiveri, Giacomo
ethz.date.deposited
2022-10-01T03:23:25Z
ethz.source
SCOPUS
ethz.eth
yes
en_US
ethz.availability
Metadata only
en_US
ethz.rosetta.installDate
2022-10-10T06:08:16Z
ethz.rosetta.lastUpdated
2023-02-07T06:59:23Z
ethz.rosetta.versionExported
true
ethz.COinS
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