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dc.contributor.author
Ottavi, Gianmarco
dc.contributor.author
Garofalo, Angelo
dc.contributor.author
Tagliavini, Giuseppe
dc.contributor.author
Conti, Francesco
dc.contributor.author
Di Mauro, Alfio
dc.contributor.author
Benini, Luca
dc.contributor.author
Rossi, Davide
dc.date.accessioned
2023-06-13T12:52:51Z
dc.date.available
2023-04-05T04:06:24Z
dc.date.available
2023-04-06T11:30:24Z
dc.date.available
2023-06-13T12:52:51Z
dc.date.issued
2023-06
dc.identifier.issn
1549-8328
dc.identifier.issn
1057-7122
dc.identifier.issn
1558-0806
dc.identifier.other
10.1109/TCSI.2023.3254810
en_US
dc.identifier.uri
http://hdl.handle.net/20.500.11850/606661
dc.description.abstract
Computationally intensive algorithms such as Deep Neural Networks (DNNs) are becoming killer applications for edge devices. Porting heavily data-parallel algorithms on resource-constrained and battery-powered devices while retaining the flexibility granted by instruction processor-based architectures poses several challenges related to memory footprint, computational throughput, and energy efficiency. Low-bitwidth and mixed-precision arithmetic have been proven to be valid strategies for tackling these problems. We present Dustin, a fully programmable compute cluster integrating 16 RISC-V cores capable of 2-to 32-bit arithmetic and all possible mixed-precision combinations. In addition to a conventional Multiple-Instruction Multiple-Data (MIMD) processing paradigm, Dustin introduces a Vector Lockstep Execution Mode (VLEM) to minimize power consumption in highly data-parallel kernels. In VLEM, a single leader core fetches instructions and broadcasts them to the 15 follower cores. Clock gating Instruction Fetch (IF) stages and private caches of the follower cores leads to 38% power reduction. The cluster, implemented in 65 nm CMOS technology, achieves a peak performance of 58 GOPS and a peak efficiency of 1.15 TOPS/W.
en_US
dc.language.iso
en
en_US
dc.publisher
IEEE
en_US
dc.subject
QNN inference
en_US
dc.subject
mixed-precision
en_US
dc.subject
SIMD
en_US
dc.subject
MIMD
en_US
dc.subject
RISC-V
en_US
dc.title
Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster With 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode
en_US
dc.type
Journal Article
dc.date.published
2023-03-15
ethz.journal.title
IEEE Transactions on Circuits and Systems I: Regular Papers
ethz.journal.volume
70
en_US
ethz.journal.issue
6
en_US
ethz.pages.start
2450
en_US
ethz.pages.end
2463
en_US
ethz.grant
Pilot using Independent Local & Open Technologies
en_US
ethz.identifier.wos
ethz.identifier.scopus
ethz.publication.place
New York, NY
en_US
ethz.publication.status
published
en_US
ethz.leitzahl
ETH Zürich::00002 - ETH Zürich::00012 - Lehre und Forschung::00007 - Departemente::02140 - Dep. Inf.technologie und Elektrotechnik / Dep. of Inform.Technol. Electrical Eng.::02636 - Institut für Integrierte Systeme / Integrated Systems Laboratory::03996 - Benini, Luca / Benini, Luca
en_US
ethz.leitzahl.certified
ETH Zürich::00002 - ETH Zürich::00012 - Lehre und Forschung::00007 - Departemente::02140 - Dep. Inf.technologie und Elektrotechnik / Dep. of Inform.Technol. Electrical Eng.::02636 - Institut für Integrierte Systeme / Integrated Systems Laboratory::03996 - Benini, Luca / Benini, Luca
ethz.grant.agreementno
101034126
ethz.grant.fundername
EC
ethz.grant.funderDoi
10.13039/501100000780
ethz.grant.program
H2020
ethz.date.deposited
2023-04-05T04:06:28Z
ethz.source
WOS
ethz.eth
yes
en_US
ethz.availability
Metadata only
en_US
ethz.rosetta.installDate
2023-06-13T12:52:52Z
ethz.rosetta.lastUpdated
2024-02-03T00:05:17Z
ethz.rosetta.versionExported
true
ethz.COinS
ctx_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.atitle=Dustin:%20A%2016-Cores%20Parallel%20Ultra-Low-Power%20Cluster%20With%202b-to-32b%20Fully%20Flexible%20Bit-Precision%20and%20Vector%20Lockstep%20Execution%20Mode&rft.jtitle=IEEE%20Transactions%20on%20Circuits%20and%20Systems%20I:%20Regular%20Papers&rft.date=2023-06&rft.volume=70&rft.issue=6&rft.spage=2450&rft.epage=2463&rft.issn=1549-8328&1057-7122&1558-0806&rft.au=Ottavi,%20Gianmarco&Garofalo,%20Angelo&Tagliavini,%20Giuseppe&Conti,%20Francesco&Di%20Mauro,%20Alfio&rft.genre=article&rft_id=info:doi/10.1109/TCSI.2023.3254810&
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