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dc.contributor.author
Bruschi, Nazareno
dc.contributor.author
Tagliavini, Giuseppe
dc.contributor.author
Garofalo, Angelo
dc.contributor.author
Conti, Francesco
dc.contributor.author
Boybat, Irem
dc.contributor.author
Benini, Luca
dc.contributor.author
Rossi, Davide
dc.date.accessioned
2023-09-06T09:22:32Z
dc.date.available
2023-08-19T03:59:41Z
dc.date.available
2023-09-06T09:22:32Z
dc.date.issued
2023
dc.identifier.isbn
979-8-3503-9624-9
en_US
dc.identifier.other
10.23919/DATE56975.2023.10137208
en_US
dc.identifier.uri
http://hdl.handle.net/20.500.11850/627335
dc.description.abstract
The demand for computation resources and energy efficiency of Convolutional Neural Networks (CNN) applications requires a new paradigm to overcome the "Memory Wall". Analog In-Memory Computing (AIMC) is a promising paradigm since it performs matrix-vector multiplications, the critical kernel of many ML applications, in-place in the analog domain within memory arrays structured as crossbars of memory cells. However, several factors limit the full exploitation of this technology, including the physical fabrication of the crossbar devices, which constrain the memory capacity of a single array. Multi-AIMC architectures have been proposed to overcome this limitation, but they have been demonstrated only for tiny and custom CNNs or performing some layers off-chip. In this work, we present the full inference of an end-to-end ResNet-18 DNN on a 512-cluster heterogeneous architecture coupling a mix of AIMC cores and digital RISC-V cores, achieving up to 20.2 TOPS. Moreover, we analyze the mapping of the network on the available non-volatile cells, compare it with state-of-the-art models, and derive guidelines for next-generation many-core architectures based on AIMC devices.
en_US
dc.language.iso
en
en_US
dc.publisher
IEEE
en_US
dc.subject
In-memory computing
en_US
dc.subject
Heterogenous systems
en_US
dc.subject
many-core architectures
en_US
dc.subject
Convolutional neural networks
en_US
dc.title
End-to-End DNN Inference on a Massively Parallel Analog In Memory Computing Architecture
en_US
dc.type
Conference Paper
dc.date.published
2023-06-02
ethz.book.title
2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)
en_US
ethz.pages.start
10137208
en_US
ethz.size
6 p.
en_US
ethz.event
26th Design, Automation and Test in Europe Conference and Exhibition (DATE 2023)
en_US
ethz.event.location
Antwerp, Belgium
en_US
ethz.event.date
April 17-19, 2023
en_US
ethz.identifier.wos
ethz.publication.place
Piscataway, NJ
en_US
ethz.publication.status
published
en_US
ethz.leitzahl
ETH Zürich::00002 - ETH Zürich::00012 - Lehre und Forschung::00007 - Departemente::02140 - Dep. Inf.technologie und Elektrotechnik / Dep. of Inform.Technol. Electrical Eng.::02636 - Institut für Integrierte Systeme / Integrated Systems Laboratory::03996 - Benini, Luca / Benini, Luca
ethz.leitzahl.certified
ETH Zürich::00002 - ETH Zürich::00012 - Lehre und Forschung::00007 - Departemente::02140 - Dep. Inf.technologie und Elektrotechnik / Dep. of Inform.Technol. Electrical Eng.::02636 - Institut für Integrierte Systeme / Integrated Systems Laboratory::03996 - Benini, Luca / Benini, Luca
ethz.date.deposited
2023-08-19T03:59:49Z
ethz.source
WOS
ethz.eth
yes
en_US
ethz.availability
Metadata only
en_US
ethz.rosetta.installDate
2023-09-06T09:22:33Z
ethz.rosetta.lastUpdated
2024-02-03T03:19:15Z
ethz.rosetta.versionExported
true
ethz.COinS
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