Performance Trade-offs Analysis of SmartNIC Architectures

Abstract

In-network packet processing utilizing SmartNICs has emerged as a promising method for enhancing the performance of distributed applications. This approach leverages packet-level parallelism and aligns with the in-network computing trend, which involves integrating energy-efficient processing cores with high-speed NICs. By offloading specific data processing tasks to the networking infrastructure instead of relying solely on the Host CPU, application latency can be reduced, and Host throughput can be maximized by effectively overlapping computation and communication. Over the past decade, several SmartNIC architectures have been developed, accompanied by corresponding APIs for programming them. Off-path SmartNICs incorporate an on-NIC PCIe switch to route packets to a multi-core SoC running an operating system, while on-path SmartNICs integrate cores along the packet communication path with packet manipulation capabilities. To analyze the trade-offs of these two architectures, we conducted a comparative analysis of on-path and off-path SmartNICs. We ported the main components of Caladan, a data plane system that incorporates interference-aware CPU scheduling, to the off-path Bluefield-2 SmartNIC. To assess its performance, we implemented IO and compute-bound tasks on top of Caladan and evaluated their throughput. We then compared the resulting throughputs with those achieved by the same tasks in PsPIN, an on-path RISC-V-based accelerator. We uncover PsPIN's superior performance while acknowledging the increased complexity associated with its application implementation. Conversely, Caladan provides a straightforward pathway for tailoring to distinct use cases and simplifying application development, albeit with potentially lower performance. These findings shed light on the intricate trade-offs and differences between performance and the intricate domains of overall system complexity and complexity of API development in off-path and on-path architectures.