Full-System Evaluation of the sPIN In-Network-Compute Architecture

Abstract

In-network-computing with SmartNICs is gaining popularity in high-performance networking for their ability to offload packet processing tasks from the CPU and their latency advantage thanks to the proximity to the network traffic without having to go through PCIe. The sPIN in-network-computing paradigm developed at ETH Zürich aims to provide a programming model for developers to build high-performance packet processing routines for on-path SmartNICs. While the paradigm has been evaluated with use cases from diverse scenarios in software and hardware simulation, it has yet to see a full E2E system-level evaluation that exercises the entire packet processing loop on hardware in the real world. In this thesis, we perform an end-to-end analysis of the sPIN paradigm by building a full-system prototype of sPIN on FPGA based on PsPIN, a cycle-accurate simulation prototype of sPIN, and Corundum, an open-source FPGA-based Ethernet NIC. We show that the resulting system FPsPIN facilitates the development and testing of sPIN handlers, allowing real-world performance and computation/communication overlap evaluations that would not have been possible with the old cycle-accurate simulation models due to the slow simulation speed and absence of a host CPU. We present various improvement suggestions to the sPIN specification, discovered through the process of building FPsPIN. In addition, we conduct a detailed performance evaluation of FPsPIN through three benchmarks implemented for the platform, showing a 50 us latency advantage, over 99% computation/communication overlap, 6.4 Gbps and 1.2 Gbps throughput in simple and complex synthetic benchmarks. The lower application throughput shows the deficiency of the packet processing cores used in FPsPIN and shows an opportunity for future research on desirable architectural features for SmartNIC cores.