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dc.contributor.author
Liu, Ling
dc.date.accessioned
2017-06-10T15:51:53Z
dc.date.available
2017-06-10T15:51:53Z
dc.date.issued
2009
dc.identifier.uri
http://hdl.handle.net/20.500.11850/65656
dc.identifier.doi
10.3929/ethz-a-006819824
dc.language.iso
en
dc.publisher
ETH, Department of Computer Science
dc.rights.uri
http://rightsstatements.org/page/InC-NC/1.0/
dc.subject
MULTIPLE DATA STREAM ARCHITECTURES + MULTIPROCESSORS (COMPUTER SYSTEMS)
dc.subject
MULTIPLE-DATA-STREAM-ARCHITEKTUREN + MULTIPROZESSOREN (COMPUTERSYSTEME)
dc.subject
PROGRAMMABLE LOGIC DEVICES, PLD (COMPUTER SYSTEMS)
dc.subject
PROGRAMMIERBARE LOGISCHE ELEMENTE (COMPUTERSYSTEME)
dc.title
A 12-core processor implementation on FPGA
dc.type
Report
dc.rights.license
In Copyright - Non-Commercial Use Permitted
dc.date.published
2011
ethz.journal.title
Technical Report / ETH Zurich, Department of Computer Science
ethz.journal.volume
646
ethz.size
13 p.
ethz.code.ddc
0 - Computer science, information & general works::004 - Data processing, computer science
ethz.notes
18 September 2009, Revised 5 October 2009. Technical Reports D-INFK.
ethz.identifier.nebis
006819824
ethz.publication.place
Zurich
ethz.publication.status
published
ethz.leitzahl
ETH Zürich::00002 - ETH Zürich::00012 - Lehre und Forschung::00007 - Departemente::02150 - Dep. Informatik / Dep. of Computer Science
ethz.leitzahl.certified
ETH Zürich::00002 - ETH Zürich::00012 - Lehre und Forschung::00007 - Departemente::02150 - Dep. Informatik / Dep. of Computer Science
ethz.date.deposited
2017-06-10T15:52:34Z
ethz.source
ECOL
ethz.source
ECIT
ethz.identifier.importid
imp59366b1868e3e85027
ethz.identifier.importid
imp593650800cd1636183
ethz.ecolpid
eth:4974
ethz.ecitpid
pub:104682
ethz.eth
yes
ethz.availability
Open access
ethz.rosetta.installDate
2017-07-19T07:14:25Z
ethz.rosetta.lastUpdated
2018-11-02T09:24:46Z
ethz.rosetta.exportRequired
true
ethz.rosetta.versionExported
true
ethz.COinS
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