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dc.contributor.author
Valente, Luca
dc.contributor.author
Nadalini, Alessandro
dc.contributor.author
Veeran, Asif Hussain Chiralil
dc.contributor.author
Sinigaglia, Mattia
dc.contributor.author
Sá, Bruno
dc.contributor.author
Wistoff, Nils
dc.contributor.author
Tortorella, Yvan
dc.contributor.author
Benatti, Simone
dc.contributor.author
Psiakis, Rafail
dc.contributor.author
Kulmala, Ari
dc.contributor.author
Mohammad, Baker
dc.contributor.author
Pinto, Sandro
dc.contributor.author
Palossi, Daniele
dc.contributor.author
Benini, Luca
dc.contributor.author
Rossi, Davide
dc.date.accessioned
2024-05-14T13:22:48Z
dc.date.available
2024-03-04T07:37:09Z
dc.date.available
2024-03-04T10:12:22Z
dc.date.available
2024-03-04T10:13:19Z
dc.date.available
2024-05-14T13:22:48Z
dc.date.issued
2024-05
dc.identifier.issn
1549-8328
dc.identifier.issn
1057-7122
dc.identifier.issn
1558-0806
dc.identifier.other
10.1109/TCSI.2024.3359044
en_US
dc.identifier.uri
http://hdl.handle.net/20.500.11850/662557
dc.description.abstract
The rapid advancement of energy-efficient parallel ultra-low-power (ULP) µcontrollers units (MCUs) is enabling the development of autonomous nano-sized unmanned aerial vehicles (nano-UAVs). These sub-10cm drones represent the next generation of unobtrusive robotic helpers and ubiquitous smart sensors. However, nano-UAVs face significant power and payload constraints while requiring advanced computing capabilities akin to standard drones, including real-time Machine Learning (ML) performance and the safe co-existence of general-purpose and real-time OSs. Although some advanced parallel ULP MCUs offer the necessary ML computing capabilities within the prescribed power limits, they rely on small main memories (<1MB) and µcontroller-class CPUs with no virtualization or security features, and hence only support simple bare-metal runtimes. In this work, we present Shaheen, a 9mm² 200mW SoC implemented in 22nm FDX technology. Differently from state-of-the-art MCUs, Shaheen integrates a Linux-capable RV64 core, compliant with the v1.0 ratified Hypervisor extension and equipped with timing channel protection, along with a low-cost and low-power memory controller exposing up to 512MB of off-chip low-cost low-power HyperRAM directly to the CPU. At the same time, it integrates a fully programmable energy- and area-efficient multi-core cluster of RV32 cores optimized for general-purpose DSP as well as reduced- and mixed-precision ML. To the best of the authors’ knowledge, it is the first silicon prototype of a ULP SoC coupling the RV64 and RV32 cores in a heterogeneous host+accelerator architecture fully based on the RISC-V ISA. We demonstrate the capabilities of the proposed SoC on a wide range of benchmarks relevant to nano-UAV applications including general-purpose DSP as well as inference and online learning of quantized DNNs. The cluster can deliver up to 90GOp/s and up to 1.8TOp/s/W on 2-bit integer kernels and up to 7.9GFLOp/s and up to 150GFLOp/s/W on 16-bit FP kernels.
en_US
dc.language.iso
en
en_US
dc.publisher
IEEE
en_US
dc.subject
Heterogeneous
en_US
dc.subject
Linux
en_US
dc.subject
low-power
en_US
dc.subject
autonomous nano-UAVs
en_US
dc.subject
RISC-V
en_US
dc.title
A Heterogeneous RISC-V Based SoC for Secure Nano-UAV Navigation
en_US
dc.type
Journal Article
dc.date.published
2024-02-07
ethz.journal.title
IEEE Transactions on Circuits and Systems I: Regular Papers
ethz.journal.volume
71
en_US
ethz.journal.issue
5
en_US
ethz.pages.start
2266
en_US
ethz.pages.end
2279
en_US
ethz.grant
Together for RISc-V Technology and ApplicatioNs
en_US
ethz.identifier.wos
ethz.identifier.scopus
ethz.publication.status
published
en_US
ethz.grant.agreementno
101095947
ethz.grant.fundername
SBFI
ethz.grant.funderDoi
10.13039/501100007352
ethz.grant.program
HE
ethz.date.deposited
2024-03-04T07:37:14Z
ethz.source
WOS
ethz.eth
yes
en_US
ethz.availability
Metadata only
en_US
ethz.rosetta.installDate
2024-05-14T13:22:49Z
ethz.rosetta.lastUpdated
2024-05-14T13:22:49Z
ethz.rosetta.exportRequired
true
ethz.rosetta.versionExported
true
ethz.COinS
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