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dc.contributor.author
Paolucci, Pier S.
dc.contributor.author
Bacivarov, Iuliana
dc.contributor.author
Goossens, Gert
dc.contributor.author
Leupers, Rainer
dc.contributor.author
Rousseau, Frederic
dc.contributor.author
Schumacher, Christoph
dc.contributor.author
Thiele, Lothar
dc.contributor.author
Vicini, Piero
dc.date.accessioned
2017-06-10T17:42:29Z
dc.date.available
2017-06-10T17:42:29Z
dc.date.issued
2013
dc.identifier.isbn
978-88-908488-0-3
dc.identifier.other
10.12837/2013T01
dc.identifier.uri
http://hdl.handle.net/20.500.11850/67600
dc.description.abstract
This is the summary of first three years of activity of the EURETILE FP7 project 247846. EURETILE investigates and implements brain-inspired and fault-tolerant foundational innovations to the system architecture of massively parallel tiled computer architectures and the corresponding programming paradigm. The execution targets are a many-tile HW platform, and a many-tile simulator. A set of SW process - HW tile mapping candidates is generated by the holistic SW tool-chain using a combination of analytic and bio-inspired methods. The Hardware dependent Software is then generated, providing OS services with maximum efficiency/minimal overhead. The many-tile simulator collects profiling data, closing the loop of the SW tool chain. Fine-grain parallelism inside processes is exploited by optimized intra-tile compilation techniques, but the project focus is above the level of the elementary tile. The elementary HW tile is a multi-processor, which includes a fault tolerant Distributed Network Processor (for inter-tile communication) and ASIP accelerators. Furthermore, EURETILE investigates and implements the innovations for equipping the elementary HW tile with high-bandwidth, low-latency brain-like inter-tile communication emulating 3 levels of connection hierarchy, namely neural columns, cortical areas and cortex, and develops a dedicated cortical simulation benchmark: DPSNN-STDP (Distributed Polychronous Spiking Neural Net with synaptic Spiking Time Dependent Plasticity). EURETILE leverages on the multi-tile HW paradigm and SW tool-chain developed by the FET-ACA SHAPES Integrated Project (2006-2009).
dc.language.iso
en
dc.publisher
EURETILE
dc.title
EURETILE 2010-2012 summary
dc.type
Report
ethz.title.subtitle
First three years of activity of the European Reference Tiled Experiment
ethz.size
56 p.
ethz.publication.place
Rom
ethz.publication.status
published
ethz.leitzahl
ETH Zürich::00002 - ETH Zürich::00012 - Lehre und Forschung::00007 - Departemente::02140 - Dep. Inf.technologie und Elektrotechnik / Dep. of Inform.Technol. Electrical Eng.::02640 - Inst. f. Technische Informatik und Komm. / Computer Eng. and Networks Lab.::03429 - Thiele, Lothar / Thiele, Lothar
ethz.leitzahl.certified
ETH Zürich::00002 - ETH Zürich::00012 - Lehre und Forschung::00007 - Departemente::02140 - Dep. Inf.technologie und Elektrotechnik / Dep. of Inform.Technol. Electrical Eng.::02640 - Inst. f. Technische Informatik und Komm. / Computer Eng. and Networks Lab.::03429 - Thiele, Lothar / Thiele, Lothar
ethz.date.deposited
2017-06-10T17:45:55Z
ethz.source
ECIT
ethz.identifier.importid
imp593650a8d8dd499502
ethz.ecitpid
pub:107538
ethz.eth
yes
ethz.availability
Metadata only
ethz.rosetta.installDate
2017-07-15T02:25:03Z
ethz.rosetta.lastUpdated
2018-11-02T09:46:31Z
ethz.rosetta.versionExported
true
ethz.COinS
ctx_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.atitle=EURETILE%202010-2012%20summary&rft.date=2013&rft.au=Paolucci,%20Pier%20S.&Bacivarov,%20Iuliana&Goossens,%20Gert&Leupers,%20Rainer&Rousseau,%20Frederic&rft.isbn=978-88-908488-0-3&rft.genre=report&rft_id=info:doi/10.12837/2013T01&rft.btitle=EURETILE%202010-2012%20summary
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