A tool for debugging JTAG

Abstract

Debuggers not hosted on the target can provide users with bare-metal access to the machine. This way, one can establish a debug session even when no operating system is present, e.g., right after the power-up. The JTAG communication protocol is often used to interface the external debuggers with the target’s infrastructure. On the Enzian research computer, such a connection between an ARM processor and the specialized adapter fails significantly limiting the debugging capabilities of Enzian’s CPU. Here, we analyze the debugging infrastructure on Enzian and find an underlying problem with the reset signal sent to the CPU. To this end, we employ JTAG adapters that expose low-level interface to the user. We also implement a JTAG controller based on an STM32 Nucleo board that directly controls the protocol signals. We demonstrate that it can successfully drive JTAG scan chains and communicate with the rest of the processor’s debug infrastructure through the Debug Access Port (DAP). Additionally, we propose an alternative method for attaching a debugger to Enzian’s CPU using the onboard programming module and the Open On-Chip Debugger (OpenOCD). The thesis highlights the importance of adhering to the standard when implementing a design as this is the cause of most errors we encountered in this work.