Evidence of Dynamic Input Capacitance of SiC Power MOSFETs

Abstract

This paper presents an evidence of dynamic input capacitance C-gg of SiC power MOSFETs. Based on the performed ramp-rate capacitance-voltage (C-V) measurements and circuit simulations, the dynamic C-gg behavior is explained by the distributed internal gate resistance defined by the on-chip gate layout network and the time-constant of charge trapping due to the present defects at the SiC-oxide interface. The ramprate-based C-gg-V-gs measurements with Vgs-ramp time of 25 mu s are compared with the standard C-gg-V-gs impedance analyzer (IA) measurements for a Si super-junction power MOSFET and two different SiC power MOSFETs. The differences between the ramp-rate- and the IA-based C-gg-V-gs measured curves are more significant for the two SiC power MOSFETs compared to the Si power MOSFET. This is attributed to SiC-oxide interface states and their time constant. The presented ramp-rate C-gg-V-gs measurement method should more accurately capture the actual C-V behavior during fast switching events.