Three-dimensional modeling of gate leakage in Si nanowire transistors

Abstract

The gate currents of Si nanowire transistors are investigated using a three-dimensional, real-space, and self-consistent Schrodinger-Poisson solver. The influence of the gate material (metal or poly-Si) and the choice of the dielectric (SiO 2 or high- kappa stacks) are studied in details. Then, the performances of nanometer-scaled triple-gate structures are analyzed with respect to ON- and OFF-currents, subthreshold swing, and threshold voltage.