Three-dimensional modeling of gate leakage in Si nanowire transistors
dc.contributor.author
Luisier, Mathieu
dc.contributor.author
Schenk, Andreas
dc.contributor.author
Fichtner, Wolfgang
dc.date.accessioned
2020-09-11T10:05:35Z
dc.date.available
2017-06-08T17:59:28Z
dc.date.available
2020-09-11T10:05:35Z
dc.date.issued
2007
dc.identifier.isbn
978-1-4244-1508-3
en_US
dc.identifier.isbn
978-1-4244-1507-6
en_US
dc.identifier.other
10.1109/IEDM.2007.4419051
en_US
dc.identifier.uri
http://hdl.handle.net/20.500.11850/7998
dc.description.abstract
The gate currents of Si nanowire transistors are investigated using a three-dimensional, real-space, and self-consistent Schrodinger-Poisson solver. The influence of the gate material (metal or poly-Si) and the choice of the dielectric (SiO 2 or high- kappa stacks) are studied in details. Then, the performances of nanometer-scaled triple-gate structures are analyzed with respect to ON- and OFF-currents, subthreshold swing, and threshold voltage.
en_US
dc.language.iso
en
en_US
dc.publisher
IEEE
en_US
dc.title
Three-dimensional modeling of gate leakage in Si nanowire transistors
en_US
dc.type
Conference Paper
dc.date.published
2008-01-04
ethz.book.title
2007 IEEE International Electron Devices Meeting
en_US
ethz.pages.start
733
en_US
ethz.pages.end
736
en_US
ethz.event
2007 IEEE International Electron Devices Meeting (IEDM 2007)
en_US
ethz.event.location
Washington, DC, USA
en_US
ethz.event.date
December 10-12, 2007
en_US
ethz.identifier.wos
ethz.publication.place
Piscataway, NJ
en_US
ethz.publication.status
published
en_US
ethz.leitzahl
03228 - Fichtner, Wolfgang
en_US
ethz.leitzahl.certified
03228 - Fichtner, Wolfgang
ethz.date.deposited
2017-06-08T17:59:33Z
ethz.source
ECIT
ethz.identifier.importid
imp59364bbe46a7574166
ethz.ecitpid
pub:18647
ethz.eth
yes
en_US
ethz.availability
Metadata only
en_US
ethz.rosetta.installDate
2017-07-19T10:48:58Z
ethz.rosetta.lastUpdated
2021-02-15T17:11:15Z
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true
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