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FPGA Design of a Coordinate Descent Data Detector for Large-Scale MU-MIMO
(2016)2016 IEEE International Symposium on Circuits and Systems (ISCAS)We propose a new, low-complexity data-detection algorithm and a corresponding high-throughput FPGA design for 3GPP LTE-based large-scale (or massive) multi-user (MU) multiple-input multiple-output (MIMO) wireless communication systems. Our algorithm performs approximate minimum mean-square error (MMSE) data detection using coordinate descent (CD), which enables near-MMSE performance at low computational complexity, even for systems with ...Conference Paper