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A quarter-rate CDR circuit is based on a dual-loop approach where sampling phases are generated by a phase-programmable PLL that is controlled by a digital DLL. Implemented in 65nm SOI CMOS, the chip occupies 0.03mm 2 and consumes 1.8mW/Gb/s. Measurements confirm 40Gb/s operation with a BER <10 -12 at a maximum frequency-offset of 400ppm. The phase relation between data and edge samples can be programmed within plusmn0.1 UI. Show more
Book title2007 IEEE International Solid-State Circuits Conference (ISSCC)
Journal / seriesDigest of Technical Papers / IEEE International Solid State Circuits Conference
Pages / Article No.
Organisational unit03386 - Jäckel, Heinz
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