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dc.contributor.author
Kang, Shin-Haeng
dc.contributor.author
Yang, Hoeseok
dc.contributor.author
Kim, Sungchan
dc.contributor.author
Bacivarov, Iuliana
dc.contributor.author
Ha, Soonhoi
dc.contributor.author
Thiele, Lothar
dc.date.accessioned
2022-08-15T12:45:46Z
dc.date.available
2017-06-11T12:07:20Z
dc.date.available
2022-08-15T12:45:46Z
dc.date.issued
2014
dc.identifier.isbn
978-3-9815370-2-4
en_US
dc.identifier.isbn
978-1-4799-3297-9
en_US
dc.identifier.other
10.7873/DATE.2014.340
en_US
dc.identifier.uri
http://hdl.handle.net/20.500.11850/88566
dc.description.abstract
This paper presents a novel mapping optimization technique for mixed critical multi-core systems with different reliability requirements. For this scope, we derived a quantitative reliability metric and presented a scheduling analysis that certifies given mixed-criticality constraints. Our framework is capable of investigating re-execution, passive replication, and modular redundancy with optimized voter placement, while typical hardening approaches consider only one or two of these techniques. The proposed technique complies with existing safety standards and is power-efficient, as demonstrated by our experiments.
en_US
dc.language.iso
en
en_US
dc.publisher
IEEE
en_US
dc.title
Reliability-Aware Mapping Optimization of Multi-Core Systems with Mixed-Criticality
en_US
dc.type
Conference Paper
dc.date.published
2014-04-21
ethz.book.title
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE)
en_US
ethz.pages.start
6800541
en_US
ethz.size
4 p.
en_US
ethz.event
Design, Automation and Test in Europe Conference and Exhibition (DATE 2014)
en_US
ethz.event.location
Dresden, Germany
en_US
ethz.event.date
March 24-28, 2014
en_US
ethz.publication.place
Piscataway, NJ
en_US
ethz.publication.status
published
en_US
ethz.leitzahl
ETH Zürich::00002 - ETH Zürich::00012 - Lehre und Forschung::00007 - Departemente::02140 - Dep. Inf.technologie und Elektrotechnik / Dep. of Inform.Technol. Electrical Eng.::02640 - Inst. f. Technische Informatik und Komm. / Computer Eng. and Networks Lab.::03429 - Thiele, Lothar (emeritus) / Thiele, Lothar (emeritus)
en_US
ethz.leitzahl.certified
ETH Zürich::00002 - ETH Zürich::00012 - Lehre und Forschung::00007 - Departemente::02140 - Dep. Inf.technologie und Elektrotechnik / Dep. of Inform.Technol. Electrical Eng.::02640 - Inst. f. Technische Informatik und Komm. / Computer Eng. and Networks Lab.::03429 - Thiele, Lothar (emeritus) / Thiele, Lothar (emeritus)
ethz.date.deposited
2017-06-11T12:07:24Z
ethz.source
ECIT
ethz.identifier.importid
imp5936523e20cba95846
ethz.ecitpid
pub:139326
ethz.eth
yes
en_US
ethz.availability
Metadata only
en_US
ethz.rosetta.installDate
2017-07-13T00:22:04Z
ethz.rosetta.lastUpdated
2018-11-02T15:37:32Z
ethz.rosetta.exportRequired
true
ethz.rosetta.versionExported
true
ethz.COinS
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