Binarization Methods for Motor-Imagery Brain–Computer Interface Classification
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Date
2020-12
Publication Type
Journal Article
ETH Bibliography
yes
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Abstract
Successful motor-imagery brain–computer interface (MI-BCI) algorithms either extract a large number of handcrafted features and train a classifier, or combine feature extraction and classification within deep convolutional neural networks (CNNs). Both approaches typically result in a set of real-valued weights, that pose challenges when targeting real-time execution on tightly resource-constrained devices. We propose methods for each of these approaches that allow transforming real-valued weights to binary numbers for efficient inference. Our first method, based on sparse bipolar random projection, projects a large number of real-valued Riemannian covariance features to a binary space, where a linear SVM classifier can be learned with binary weights too. By tuning the dimension of the binary embedding, we achieve almost the same accuracy in 4-class MI (≤1.27% lower) compared to models with float16 weights, yet delivering a more compact model with simpler operations to execute. Second, we propose to use memory-augmented neural networks (MANNs) for MI-BCI such that the augmented memory is binarized. Our method replaces the fully connected layer of CNNs with a binary augmented memory using bipolar random projection, or learned projection. Our experimental results on EEGNet, an already compact CNN for MI-BCI, show that it can be compressed by 1.28x at iso-accuracy using the random projection. On the other hand, using the learned projection provides 3.89% higher accuracy but increases the memory size by 28.10x.
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published
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Volume
10 (4)
Pages / Article No.
567 - 577
Publisher
IEEE
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Subject
Convolutional Neural Networks; Sparse random projection; Support Vector Machine; memory-augmented neural networks
Organisational unit
03996 - Benini, Luca / Benini, Luca
Notes
Funding
ETH-09 18-2 - Human Augmentation Interfaces (ETHZ)
780215 - Computation-in-memory architecture based on resistive devices (EC)
780215 - Computation-in-memory architecture based on resistive devices (EC)