Journal: IEEE Journal on Emerging and Selected Topics in Circuits and Systems

Abbreviation

IEEE j. emerg. sel. top. circuits syst.

Publisher

IEEE

Journal Volumes

ISSN

2156-3357

Description

Filters

2012 - 2019162020 - 202517
Reset filters

Search Results

Publications 1 - 10 of 33
  • Decentralized Baseband Processing for Massive MU-MIMO Systems
    Item type: Journal Article
    Li, Kaipeng; Sharan, Rishi R.; Chen, Yujun; et al. (2017)
    IEEE Journal on Emerging and Selected Topics in Circuits and Systems
    Achieving high spectral efficiency in realistic massive multi-user (MU) multiple-input multiple-output (MIMO) wireless systems requires computationally complex algorithms for data detection in the uplink (users transmit to base-station) and beamforming in the downlink (base-station transmits to user). Most existing algorithms are designed to be executed on centralized computing hardware at the base-station (BS), which results in prohibitive complexity for systems with hundreds or thousands of antennas and generates raw baseband data rates that exceed the limits of current interconnect technology and chip I/O interfaces. This paper proposes a novel decentralized baseband processing architecture that alleviates these bottlenecks by partitioning the BS antenna array into clusters, each associated with independent radio-frequency chains, analog and digital modulation circuitry, and computing hardware. For this architecture, we develop novel decentralized data detection and beamforming algorithms that only access local channel-state information and require low communication bandwidth among the clusters. We study the associated tradeoffs between error-rate performance, computational complexity, and interconnect bandwidth, and we demonstrate the scalability of our solutions for massive MU-MIMO systems with thousands of BS antennas using reference implementations on a graphics processing unit (GPU) cluster.
  • Guest Editorial: Artificial Intelligence for 5G and Beyond 5G: Implementations, Algorithms, and Optimizations
    Item type: Other Journal Item
    Zhang, Chuan; Ueng, Yeong-Luh; Studer, Christoph; et al. (2020)
    IEEE Journal on Emerging and Selected Topics in Circuits and Systems
    This Special Issue of the IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS) is dedicated to demonstrating the latest research progress on artificial intelligence for 5G and beyond 5G (B5G) with respect to implementations, algorithms, and optimizations.
  • EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerators
    Item type: Journal Article
    Cavigelli, Lukas Arno Jakob; Rutishauser, Georg; Benini, Luca (2019)
    IEEE Journal on Emerging and Selected Topics in Circuits and Systems
  • Optimizing Temporal Convolutional Network Inference on FPGA-Based Accelerators
    Item type: Journal Article
    Carreras, Marco; Deriu, Gianfranco; Raffo, Luigi; et al. (2020)
    IEEE Journal on Emerging and Selected Topics in Circuits and Systems
    Convolutional Neural Networks (CNNs) are extensively used in a wide range of applications, commonly including computer vision tasks like image and video classification, recognition and segmentation. Recent research results demonstrate that multi-layer (deep) network involving mono-dimensional convolutions and dilation can be effectively used in time series and sequences classification and segmentation, as well as in tasks involving sequence modeling. These structures, commonly referred to as Temporal Convolutional Networks (TCNs), represent an extremely promising alternative to recurrent architectures, commonly used across a broad range of sequence modeling tasks. While FPGA based inference accelerators for classic CNNs are widespread, literature is lacking in a quantitative evaluation of their usability on inference for TCN models. In this paper we present such an evaluation, considering a CNN accelerator with specific features supporting TCN kernels as a reference and a set of state-of-the-art TCNs as a benchmark. Experimental results show that, during TCN execution, operational intensity can be critical for the overall performance. We propose a convolution scheduling based on batch processing that can boost efficiency up to 96% of theoretical peak performance. Overall we can achieve up to 111,8 GOPS/s and a power efficiency of 33,8 GOPS/s/W on an Ultrascale+ ZU3EG (up to 10x speedup and 3x power efficiency improvement with respect to pure software implementation).
  • Incremental Learning of Hand Symbols Using Event-Based Cameras
    Item type: Journal Article
    Lungu, Iulia A.; Liu, Shih-Chii; Delbruck, Tobi (2019)
    IEEE Journal on Emerging and Selected Topics in Circuits and Systems
  • Improving Resilience to Timing Errors by Exposing Variability Effects to Software in Tightly-Coupled Processor Clusters
    Item type: Journal Article
    Rahimi, Abbas; Cesarini, Daniele; Marongiu, Andrea; et al. (2014)
    IEEE Journal on Emerging and Selected Topics in Circuits and Systems
  • Energy-Quality Scalable Circuits and Systems for Sensing and Computing: From Approximate to Communication-Inspired and Learning-Based
    Item type: Other Journal Item
    Alioto, Massimo; De, Vivek; Marongiu, Andrea (2018)
    IEEE Journal on Emerging and Selected Topics in Circuits and Systems
  • A Heterogeneous In-Memory Computing Cluster for Flexible End-to-End Inference of Real-World Deep Neural Networks
    Item type: Journal Article
    Garofalo, Angelo; Ottavi, Gianmarco; Conti, Francesco; et al. (2022)
    IEEE Journal on Emerging and Selected Topics in Circuits and Systems
    Deployment of modern TinyML tasks on small battery-constrained IoT devices requires high computational energy efficiency. Analog In-Memory Computing (IMC) using non-volatile memory (NVM) promises major efficiency improvements in deep neural network (DNN) inference and serves as on-chip memory storage for DNN weights. However, IMC's functional flexibility limitations and their impact on performance, energy, and area efficiency are not yet fully understood at the system level. To target practical end-to-end loT applications, IMC arrays must be enclosed in heterogeneous programmable systems, introducing new system-level challenges which we aim at addressing in this work. We present a heterogeneous tightly-coupled clustered architecture integrating 8 RISC-V cores, an in-memory computing accelerator (IMA), and digital accelerators. We benchmark the system on a highly heterogeneous workload such as the Bottleneck layer from a MobileNetV2, showing 11.5x performance and 9.5x energy efficiency improvements, compared to highly optimized parallel execution on the cores. Furthermore, we explore the requirements for end-to-end inference of a full mobile-grade DNN (MobileNetV2) in terms of IMC array resources, by scaling up our heterogeneous architecture to a multi-array accelerator. Our results show that our solution, on the end-to-end inference of the MobileNetV2, is one order of magnitude better in terms of execution latency than existing programmable architectures and two orders of magnitude better than state-of-the-art heterogeneous solutions integrating in-memory computing analog cores.
  • EMG-Based Gestures Classification Using a Mixed-Signal Neuromorphic Processing System
    Item type: Journal Article
    Ma, Yongqiang; Chen, Badong; Ren, Pengju; et al. (2020)
    IEEE Journal on Emerging and Selected Topics in Circuits and Systems
    The rapid increase of wearable sensor devices poses new challenges for implementing continuous real-time processing of physiological data. Neuromorphic sensory-processing devices can enable both the measurement of bio-signals and their processing locally in compact embedded wearable systems. In particular, mixed-signal spiking neural networks implemented on neuromorphic processors can be integrated directly with the sensors to extract temporal data-streams in real-time with very low power consumption. In this work, we present a neuromorphic approach for classifying spatio-temporal data from electromyography (EMG) signals, which paves the way toward the realization of compact wearable solutions for neuroprosthetic control. Here we extend previously proposed delta-encoding methods to transform bio-signals into spike trains and use a spiking Recurrent Neural Network (SRNN) architecture to extract features from them. The SRNN was first simulated in software to find the optimal set of hyperparameters, and then validated on the neuromorphic hardware, with a difference in the performance of less than 2%. We describe how biologically plausible mechanisms such as Spike-Timing Dependent Plasticity (STDP) and soft Winner-Take-All (WTA) networks can be exploited to classify the EMG signals and show how their combined use in EMG data classification achieves competitive results with different datasets. Specifically, the classification performance for the Roshambo EMG dataset, which has three different classes, is above 85%, and for the basic finger movements dataset from the Ninapro database, which has eight different classes, reaches 55% accuracy. © 2020 IEEE.
  • A Reconfigurable DT Delta Sigma Modulator for Multi- Standard 2G/3G/4G Wireless Receivers
    Item type: Journal Article
    Bettini, Luca; Christen, Thomas; Burger, Thomas; et al. (2015)
    IEEE Journal on Emerging and Selected Topics in Circuits and Systems
Publications 1 - 10 of 33