Spatzformer: An Efficient Reconfigurable Dual-Core RISC-V V Cluster for Mixed Scalar-Vector Workloads
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Date
2024
Publication Type
Conference Paper
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yes
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Abstract
Multi-core vector processor architectures excel in handling computationally intensive vectorizable tasks but struggle to achieve optimal resource utilization when facing sequential and control tasks that cannot be vectorized. This work presents Spatzformer, the first reconfigurable RISC-V V (RVV) architecture developed from a baseline open-source dual-core cluster based on Snitch scalar cores augmented with compact Spatz vector units. Spatzformer operates in two distinct modes: split mode, working as a dual-core vector architecture to handle vectorizable tasks concurrently, and merge mode, where two vector units are driven by a single scalar core, allowing the remaining scalar core to handle non-vectorizable control tasks. We implement Spatzformer in a 12-nm technology node and characterize the cost of the added architectural reconfigurability. We show that merge mode accelerates mixed scalar-vector kernels by up to 1.8x compared to split mode. Moreover, it accelerates the vector kernels that require fine-grained synchronization (such as FFT) by up to 20% with respect to the baseline. The reconfigurability features do not degrade the architecture's maximum frequency (1.2 GHz, TT, 0.8 V, 25 degrees C) and have a negligible area impact (+1.4%), with a worst-case energy efficiency drop of only 7% with respect to the non-reconfigurable baseline.
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published
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Book title
2024 IEEE 35th International Conference on Application-specific Systems, Architectures and Processors (ASAP)
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Volume
Pages / Article No.
172 - 173
Publisher
IEEE
Event
35th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP 2024)
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Methods
Software
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Date collected
Date created
Subject
RISC-V; Vector; Reconfigurable; Processor
Organisational unit
03996 - Benini, Luca / Benini, Luca
Notes
Conference Presentation held on July 25, 2024.