64-kB 65-nm GC-eDRAM With Half-Select Support and Parallel Refresh Technique
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Date
2022
Publication Type
Journal Article
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yes
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Abstract
Gain-cell-embedded DRAM (GC-eDRAM) is an attractive alternative to traditional 6T SRAM, as it offers higher density, lower leakage power, and two-ported functionality. However, its refresh requirement also results in power consumption and memory access limitations. In this letter, we present a GC-eDRAM architecture designed to overcome the refresh disadvantages using a novel technique for improving the availability of the memory. In addition, by using a read-before-write mechanism, half select is supported. The macro avoids the need for supply boosting by employing 3T-1C bitcells and also integrates a replica bit line for optimal access timing to improve performance and power consumption. A 64- kB GC-eDRAM macro was fabricated in a 65- nm process technology, providing a 40% area reduction compared to a 6T SRAM cell, while achieving a 99.99% bit yield with a 16 mu s retention time.
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Publication status
published
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Journal / series
Volume
5
Pages / Article No.
170 - 173
Publisher
IEEE
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Edition / version
Methods
Software
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Date collected
Date created
Subject
eDRAM; embedded memory; gain cell; refresh; retention time; SRAM; system architecture
Organisational unit
03996 - Benini, Luca / Benini, Luca
Notes
Funding
180625 - Heterogeneous Computing Systems with Customized Accelerators (SNF)