An Iterative Method for Mapping-Aware Frequency Regulation in Dataflow Circuits
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Date
2023
Publication Type
Conference Paper
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yes
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Abstract
Dataflow circuits promise to overcome the scheduling limitations of standard HLS solutions. However, their performance suffers due to timing overheads caused by their handshake communication protocol. Current pipelining solutions fail to account for logic optimizations that occur during FPGA synthesis, thus producing over-conservative results. In this work, we develop an FPGA mapping-aware timing regulation technique for dataflow circuits; it relies on FPGA synthesis information to identify the circuit’s critical path and optimize it through register placement. Our dataflow circuits Pareto-dominate state-of-the-art solutions, with up to 29% and 21% execution time and area reduction, respectively.
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published
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Book title
2023 60th ACM/IEEE Design Automation Conference (DAC)
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Pages / Article No.
10247686
Publisher
IEEE
Event
60th ACM/IEEE Design Automation Conference (DAC 2023)
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Software
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Organisational unit
09761 - Josipović, Lana / Josipović, Lana
Notes
Conference lecture held on July 12, 2023.