A Sub-mW Dual-Engine ML Inference System-on-Chip for Complete End-to-End Face-Analysis at the Edge
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2021
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Conference Paper
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Abstract
Smart vision-based IoT applications operate on a sub-mW power budget while requiring power-hungry always-on image processing capabilities. This work presents a system-on-chip (SoC) that enables hierarchical processing of face analysis under multiple sub-mW operating scenarios using two tightly coupled machine learning (ML) accelerators. A dynamically scalable binary decision tree (BDT) engine for face detection (FD) allows triggering a multi-precision convolutional neural network (CNN) engine for subsequent face recognition (FR). The 22nm SoC can therefore dynamically trade-off image analysis depth, frames-per-second (FPS), accuracy, and power consumption. It implements complete end-to-end edge processing, enabling always-on FD and FR within the tight 1mW power budget of a 55mm diameter indoor solar panel. The SoC achieves >2x improvement in energy efficiency at iso-accuracy and iso-FPS over state-of-the-art (SoA) systems. ©2021 JSAP
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published
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2021 Symposium on VLSI Circuits
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IEEE
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Symposia on VLSI Technology and Circuits (VLSI 2021)
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03996 - Benini, Luca / Benini, Luca