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Hong Chul Nam


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Nam

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Hong Chul

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0000-0002-6496-5093

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Publications 1 - 2 of 2
  • FlowSim: An Invertible Generative Network for Efficient Statistical Analysis under Process Variations
    Item type: Conference Paper
    Park, Chanwoo; Nam, Hong Chul; Park, Jihun; et al. (2023)
    2023 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)
    The analysis of statistical variation in circuits or devices, resulting from process, voltage, and temperature (PVT) variations, is a critical aspect of ensuring high yield and accurate high-sigma analysis in semiconductor fabrication. As the industry progresses toward nanometer technologies, process variation becomes a significant challenge, necessitating the development of effective statistical models. Traditional Monte Carlo simulations, however, struggle to scale with the increasing number of process variables, leading to an exponential growth in the required simulations. In response to this challenge, we introduce FlowSim, a novel approach that employs density estimation to accurately perform yield and high-sigma analysis with a significantly reduced number of simulations. This approach offers a unique solution to the scalability issues faced by conventional Monte Carlo simulations, providing over a 100x decrease in the number of required simulations while maintaining a prediction error below 5% across all statistical metrics of circuit performance.
  • Victima: Drastically Increasing Address Translation Reach by Leveraging Underutilized Cache Resources
    Item type: Conference Paper
    Kanellopoulos, Constantinos; Nam, Hong Chul; Bostanci, Nisa; et al. (2023)
    MICRO '23: Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture
    Address translation is a performance bottleneck in data-intensive workloads due to large datasets and irregular access patterns that lead to frequent high-latency page table walks (PTWs). PTWs can be reduced by using (i) large hardware TLBs or (ii) large software-managed TLBs. Unfortunately, both solutions have significant drawbacks: increased access latency, power and area (for hardware TLBs), and costly memory accesses, the need for large contiguous memory blocks, and complex OS modifications (for software-managed TLBs). We present Victima, a new software-transparent mechanism that drastically increases the translation reach of the processor by leveraging the underutilized resources of the cache hierarchy. The key idea of Victima is to repurpose L2 cache blocks to store clusters of TLB entries, thereby providing an additional low-latency and high-capacity component that backs up the last-level TLB and thus reduces PTWs. Victima has two main components. First, a PTW cost predictor (PTW-CP) identifies costly-to-translate addresses based on the frequency and cost of the PTWs they lead to. Leveraging the PTW-CP, Victima uses the valuable cache space only for TLB entries that correspond to costly-to-translate pages, reducing the impact on cached application data. Second, a TLB-aware cache replacement policy prioritizes keeping TLB entries in the cache hierarchy by considering (i) the translation pressure (e.g., last-level TLB miss rate) and (ii) the reuse characteristics of the TLB entries. Our evaluation results show that in native (virtualized) execution environments Victima improves average end-to-end application performance by 7.4% (28.7%) over the baseline four-level radix-tree-based page table design and by 6.2% (20.1%) over a state-of-the-art software-managed TLB, across 11 diverse data-intensive workloads. Victima delivers similar performance as a system that employs an optimistic 128K-entry L2 TLB, while avoiding the associated area and power overheads. Victima (i) is effective in both native and virtualized environments, (ii) is completely transparent to application and system software, (iii) unlike large software-managed TLBs, does not require contiguous physical allocations, (iv) is compatible with modern large page mechanisms and (iv) incurs very small area and power overheads of and , respectively, on a modern high-end CPU. The source code of Victima is freely available at https://github.com/CMU-SAFARI/Victima.
Publications 1 - 2 of 2