Improving the Accuracy of Analog-Based In-Memory Computing Accelerators Post-Training
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2024
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Conference Paper
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Abstract
Analog-Based In-Memory Computing (AIMC) inference accelerators can be used to efficiently execute Deep Neural Network (DNN) inference workloads. However, to mitigate accuracy losses, due to circuit and device non-idealities, HardwareAware (HWA) training methodologies must be employed. These typically require significant information about the underlying hardware. In this paper, we propose two Post-Training (PT) optimization methods to improve accuracy after training is performed. For each crossbar, the first optimizes the conductance range of each column, and the second optimizes the input, i.e, Digital-to-Analog Converter (DAC), range. It is demonstrated that, when these methods are employed, the complexity during training, and the amount of information about the underlying hardware can be reduced, with no notable change in accuracy (=0.1%) when finetuning the pretrained RoBERTa transformer model for all General Language Understanding Evaluation (GLUE) benchmark tasks. Additionally, it is demonstrated that further optimizing learned parameters PT improves accuracy.
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published
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2024 IEEE International Symposium on Circuits and Systems (ISCAS)
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IEEE
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IEEE International Symposium on Circuits and Systems (ISCAS 2024)
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Subject
In-Memory Computing; Training; Optimization