TransLib: A Library to Explore Transprecision Floating-Point Arithmetic on Multi-Core IoT End-Nodes
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Date
2023
Publication Type
Conference Paper
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yes
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Abstract
Reduced-precision floating-point (FP) arithmetic is being widely adopted to reduce memory footprint and execution time on battery-powered Internet of Things (IoT) end-nodes. However, reduced precision computations must meet end-do-end precision constraints to be acceptable at the application level. This work introduces TransLib(1), an open-source kernel library based on transprecision computing principles, which provides knobs to exploit different FP data types (i.e., float, float16, and bfloat16), also considering the trade-off between homogeneous and mixed-precision solutions. We demonstrate the capabilities of the proposed library on PULP, a 32-bit microcontroller (MCU) coupled with a parallel, programmable accelerator. On average, TransLib kernels achieve an IPC of 0.94 and a speed-up of 1.64x using 16-bit vectorization. The parallel variants achieve a speed-up of 1.97x, 3.91x, and 7.59x on 2, 4, and 8 cores, respectively. The memory footprint reduction is between 25% and 50%. Finally, we show that mixed-precision variants increase the accuracy by 30x at the cost of 2.09x execution time and 1.35x memory footprint compared to float16 vectorized.
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published
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Book title
2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)
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Pages / Article No.
10136916
Publisher
IEEE
Event
26th Design, Automation and Test in Europe Conference and Exhibition (DATE 2023)
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Software
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Subject
Transprecision computing; IoT end-nodes; Parallel programming; SIMD vectorization
Organisational unit
03996 - Benini, Luca / Benini, Luca