Role of Non-Idealities in III-V/Si and All III-V Tunnel Field Effect Transistors
Open access
Autor(in)
Datum
2018-05Typ
- Doctoral Thesis
ETH Bibliographie
yes
Altmetrics
Abstract
Energy scaling of integrated circuits has hit a roadblock as the operating
voltage of the MOSFET-based solid state switches has attained a
minimum possible value. The thermionic emission mechanism, which
governs the switching of the Metal-Oxide Semiconductor Field Effect
Transistors (MOSFETs), does not allow to achieve subthreshold swing
below 60 mV/decade at room temperature, thus establishing a lower
limit on the operating voltage. Tunnel Field Effect Transistors (TFETs)
which operate on the principle of field modulation of Band-to-band
Tunneling (BTBT) can deliver a subthreshold swing less than 60
mV/dec. Therefore, TFETs are considered as a potential candidate
to replace MOSFETs as solid-state switches to achieve further scaling
of the supply voltage. However, the swing of a TFET is degraded by
non-idealities such as traps, band tails, interface roughness, etc., which
are inevitably present. To understand the effect of the non-idealities
on the TFETs, physics-based models have been developed in this work
and implemented in the Technology Computer Aided Design (TCAD)
simulator Synopsys Sentaurus Device.
Simulations show that channel quantization reduces the on-current
of the TFET which is confirmed by comparison with the experimental
transfer characteristics of InAs/Si TFETs. Also, interface roughness
and band tails are found to degrade the swing. TCAD analysis of experimental
InAs/Si and all-III-V TFETs has confirmed that, maximum
degradation of the swing results from the traps at the hetero-interface
and the oxide interface. Our simulation set-up has achieved good
agreement with the experimentally obtained temperature dependent as
well as VDS dependent transfer characteristics which confirms reliability
of the set-up. Using this set-up, we have shown that, scaling of the
nanowire diameter below 20nm and alignment of the gate with InAs/Si
hetero-interface enables InAs/Si TFETs to deliver sub-60mV/dec swing
even in the presence of traps.
Additionally, ab-initio modeling is performed to better understand
the origin of traps at InAs/Si interface. It reveals that dangling bonds
on As atoms at the interface are primarily responsible for the high Dit. Mehr anzeigen
Persistenter Link
https://doi.org/10.3929/ethz-b-000269371Publikationsstatus
publishedExterne Links
Printexemplar via ETH-Bibliothek suchen
Verlag
ETH ZurichThema
trap-assisted tunneling (TAT); Tunnel FETs; trap-tolerance; Surface Roughness; band-to-band tunnelingOrganisationseinheit
03925 - Luisier, Mathieu / Luisier, Mathieu
ETH Bibliographie
yes
Altmetrics