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A 72mW 0.03mm2 Inductorless 40Gb/s CDR in 65nm SOI CMOS
(2007)Digest of Technical Papers / IEEE International Solid State Circuits Conference ~ 2007 IEEE International Solid-State Circuits Conference (ISSCC)A quarter-rate CDR circuit is based on a dual-loop approach where sampling phases are generated by a phase-programmable PLL that is controlled by a digital DLL. Implemented in 65nm SOI CMOS, the chip occupies 0.03mm 2 and consumes 1.8mW/Gb/s. Measurements confirm 40Gb/s operation with a BER <10 -12 at a maximum frequency-offset of 400ppm. The phase relation between data and edge samples can be programmed within plusmn0.1 UI.Other Conference Item -
A 16Gb/s Source-Series Terminated Transmitter in 65nm CMOS SOI
(2007)Digest of Technical Papers / IEEE International Solid State Circuits Conference ~ 2007 IEEE International Solid-State Circuits Conference (ISSCC)A half-rate source-series terminated TX, operating at data-rates up to 16Gb/s, targets chip-to-chip on-board interconnects. The TX features a 4-tap FFE, tunable termination, and clock-cleanup circuitry for low duty-cycle distortion, and is capable of driving loads referenced to a variable termination voltage, including Gnd, V DD , and V DD /2. Implemented in 65nm SOI, it occupies an area of 230 times 56mum 2 and draws 57.5mA from a 1V ...Other Conference Item -
A Linear Uplink WCDMA Modulator with 156dBc/Hz Downlink SNR
(2007)Digest of Technical Papers / IEEE International Solid State Circuits Conference ~ 2007 IEEE International Solid-State Circuits Conference (ISSCC)A linearity-boosting technique for upconversion mixers enables a 0.13 μm CMOS WCDMA modulator to achieve -49dBc ACLR and -l56dBc/Hz SNR. The chip consumes 113mW from a 1.2V supply. It is suitable for SAW-filter-free TX implementations. Results show that this technique improves the mixer IIP3 by 6dB.Other Conference Item -
A 0.13μm CMOS EDGE/UMTS/WLAN Tri-Mode ΔΣ ADC with -92dB THD
(2007)Digest of Technical Papers / IEEE International Solid State Circuits Conference ~ 2007 IEEE International Solid-State Circuits Conference (ISSCC)A 2-2 cascaded multi-standard DeltaSigma modulator achieves a OR of 88/79/67dB in EDGE/UMTS/WLAN mode, respectively. With a high linearity of -92dB THD and 34dBm IIP3 for EDGE, this ADC is suitable for wireless applications. Implemented in 0.13 μm CMOS and occupying 0.4mm 2 , the modulator covers 0.1-to-10MHz signal bandwidth with scalable power consumption between 2.9 and 20.5mW from a 1.2V supply.Other Conference Item -
Triazole Based Chelating Systems for the Tc/Re-Tricarbonyl Core
(2007)Journal of Labelled Compounds and RadiopharmaceuticalsOther Conference Item -
Salmonella typhimurium exploits inflammation to compete with the intestinal microbiota
(2007)International Journal of Medical MicrobiologyOther Conference Item -
182Hf-182W chronometry and the origin and evolution of planetary bodies
(2007)Lunar and planetary institute contribution : Workshop program and abstracts ~ Workshop on the Chronology of Meteorites and the Early Solar System : Workshop Program and AbstractsOther Conference Item -
RFIDice
(2007)Proceedings of 4th International Symposium on Pervasive Gaming Applications (PerGames'07)Other Conference Item -
Influence of dietary benzoic acid on bone stability and bone metabolism in growing/finishing pigs
(2007)Proceedings of the Society of Nutrition Physiology = Berichte der Gesellschaft für Ernährungsphysiologie ~ 61. Tagung vom 6.-80.03.2007 in Göttingen : - Uebersichtsreferat (Review) - Kurzfassungen der Originalmitteilungen (Abstracts) - Workshop-BeiträgeOther Conference Item -
Multi-goal Genetic Algorithm Based SAR Optimization of CAD Derived Mobile Device Terminals
(2007)29th Bioelectromagnetics Society annual meeting abstract collection 2007Other Conference Item