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Date
2005-06Type
- Conference Paper
ETH Bibliography
yes
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Abstract
Model checking techniques applied to large industrial circuits suffer from the state space explosion problem. A major technique to address this problem is abstraction. The most commonly used abstraction technique for hardware verification is localization reduction, which removes latches that are not relevant to the property. However, localization reduction fails to reduce the size of the model if the property actually depends on most of the latches. This paper proposes to use predicate abstraction for verifying RTL Verilog, a technique successfully used for software verification. The main challenge when using predicate abstraction is the discovery of suitable predicates. We propose to use weakest preconditions of Verilog statements in order to obtain new predicates during abstraction refinement. This technique has not been applied to circuits before. On benchmarks taken from an industrial microprocessor, we successfully verified safety properties with more than 32,000 latches in the cone of influence. We compare the performance of our technique with a modern model checker that implements localization reduction. Show more
Publication status
publishedExternal links
Book title
DAC '05: Proceedings of the 42nd annual Design Automation ConferencePages / Article No.
Publisher
Association for Computing MachineryEvent
Subject
Predicate Abstraction; Verilog; SATOrganisational unit
03686 - Kröning, Daniel
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ETH Bibliography
yes
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