Abstract
The multi-pumping resource sharing technique can overcome the limitations commonly found in single-clocked FPGA designs by allowing hardware components to operate at a higher clock frequency than the surrounding system. However, this optimization cannot be expressed in high levels of abstraction, such as HLS, requiring the use of hand-optimized RTL. In this paper we show how to leverage multiple clock domains for computational subdomains on reconfigurable devices through data movement analysis on high-level programs.We offer a novel view on multi-pumping as a compiler optimization - a superclass of traditional vectorization. As multiple data elements are fed and consumed, the computations are packed temporally rather than spatially. The optimization is applied automatically using an intermediate representation that maps high-level code to HLS. Internally, the optimization injects modules into the generated designs, incorporating RTL for finegrained control over the clock domains. We obtain a reduction of resource consumption by up to 50% on critical components and 23% on average. For scalable designs, this can enable further parallelism, increasing overall performance. Show more
Publication status
publishedExternal links
Book title
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided DesignPages / Article No.
Publisher
Association for Computing MachineryEvent
Organisational unit
03950 - Hoefler, Torsten / Hoefler, Torsten
Funding
955606 - DEEP- Software for Exascale Archtiectures (EC)
101002047 - Productive Spatial Accelerator Programming (EC)
185778 - Empowering Computational Science using Data-Centric Programming (SNF)
More
Show all metadata
ETH Bibliography
yes
Altmetrics