Abstract
This article presents analytical tools for high-level design of the leapfrog (LF) control-bounded analog-to-digital converter (CBADC). We derive closed-form design equations for parameterizing the analog system for a target signal-to-noise ratio (SNR) and bandwidth. Furthermore, we show how the parameterization can be modified to compensate for finite amplifier gain-bandwidth product (GBWP) and to control the signal swing at different nodes of the system. Behavioral circuit simulations are used to compare the LF CBADC to relevant continuous-time sigma–delta modulators (CT- ΣΔ Ms) in terms of nominal performance and sensitivity to component variations, clock jitter, and finite GBWP. Simulations show that the nominal performance of the LF is similar to that of a CT- ΣΔ M of the same loop-filter order and with the same number of quantization levels. The simple, modular structure, analytical stability guarantee, and single-bit quantizers make the LF an interesting alternative to conventional CT- ΣΔ Ms. Show more
Publication status
publishedExternal links
Journal / series
IEEE Transactions on Very Large Scale Integration (VLSI) SystemsVolume
Pages / Article No.
Publisher
IEEESubject
Analog-to-digital conversion; control-bounded conversion; leapfrog (LF) analog-to-digital converter (ADC); sigma-delta modulationOrganisational unit
03568 - Loeliger, Hans-Andrea / Loeliger, Hans-Andrea
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