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dc.contributor.author
Rubino, Arianna
dc.contributor.author
Cartiglia, Matteo
dc.contributor.author
Payvand, Melika
dc.contributor.author
Indiveri, Giacomo
dc.date.accessioned
2024-01-31T14:31:47Z
dc.date.available
2024-01-26T08:43:26Z
dc.date.available
2024-01-31T14:31:47Z
dc.date.issued
2023
dc.identifier.isbn
979-8-3503-3267-4
en_US
dc.identifier.isbn
979-8-3503-3268-1
en_US
dc.identifier.other
10.1109/aicas57966.2023.10168620
en_US
dc.identifier.uri
http://hdl.handle.net/20.500.11850/655520
dc.description.abstract
Mixed-signal neuromorphic systems represent a promising solution for solving extreme-edge computing tasks without relying on external computing resources. Their spiking neural network circuits are optimized for processing sensory data on-line in continuous-time. However, their low precision and high variability can severely limit their performance. To address this issue and improve their robustness to inhomogeneities and noise in both their internal state variables and external input signals, we designed on-chip learning circuits with short-term analog dynamics and long-term tristate discretization mechanisms. An additional hysteretic stop-learning mechanism is included to improve stability and automatically disable weight updates when necessary, to enable continuous always-on learning. We designed a spiking neural network with these learning circuits in a prototype chip using a 180 nm CMOS technology. Simulation and silicon measurement results from the prototype chip are presented. These circuits enable the construction of large-scale spiking neural networks with online learning capabilities for real-world edge computing tasks.
en_US
dc.language.iso
en
en_US
dc.publisher
IEEE
en_US
dc.subject
Always-on learning
en_US
dc.subject
Edge-computing
en_US
dc.subject
On-chip learning online
en_US
dc.subject
SNN
en_US
dc.subject
Hysteresis
en_US
dc.subject
Tristability
en_US
dc.title
Neuromorphic analog circuits for robust on-chip always-on learning in spiking neural networks
en_US
dc.type
Conference Paper
dc.date.published
2023-07-07
ethz.book.title
2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS)
en_US
ethz.pages.start
10168620
en_US
ethz.size
5 p.
en_US
ethz.event
5th International Conference on Artificial Intelligence Circuits and Systems (AICAS 2023)
en_US
ethz.event.location
Hangzhou, China
en_US
ethz.event.date
June 11-13, 2023
en_US
ethz.grant
BEOL technology platform based on ferroelectric synaptic devices for advanced neuromorphic processors
en_US
ethz.publication.place
Piscataway, NJ
en_US
ethz.publication.status
published
en_US
ethz.leitzahl
ETH Zürich::00002 - ETH Zürich::00012 - Lehre und Forschung::00007 - Departemente::02140 - Dep. Inf.technologie und Elektrotechnik / Dep. of Inform.Technol. Electrical Eng.::02533 - Institut für Neuroinformatik / Institute of Neuroinformatics::09699 - Indiveri, Giacomo / Indiveri, Giacomo
en_US
ethz.leitzahl.certified
ETH Zürich::00002 - ETH Zürich::00012 - Lehre und Forschung::00007 - Departemente::02140 - Dep. Inf.technologie und Elektrotechnik / Dep. of Inform.Technol. Electrical Eng.::02533 - Institut für Neuroinformatik / Institute of Neuroinformatics::09699 - Indiveri, Giacomo / Indiveri, Giacomo
en_US
ethz.grant.agreementno
871737
ethz.grant.fundername
EC
ethz.grant.funderDoi
10.13039/501100000780
ethz.grant.program
H2020
ethz.date.deposited
2024-01-26T08:43:27Z
ethz.source
FORM
ethz.eth
yes
en_US
ethz.availability
Metadata only
en_US
ethz.rosetta.installDate
2024-01-31T14:31:49Z
ethz.rosetta.lastUpdated
2024-01-31T14:31:49Z
ethz.rosetta.versionExported
true
ethz.COinS
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