Suppressing Spurious Dynamism of Dataflow Circuits via Latency and Occupancy Balancing
Open access
Date
2024-04Type
- Conference Paper
ETH Bibliography
yes
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Abstract
Dataflow circuits produced via high-level synthesis (HLS) adapt their schedule at runtime to unpredictable data and control outcomes, thus promising superior performance to standard HLS solutions. However, their distributed handshake mechanism is extremely resource-expensive-there is a clear benefit in simplifying or removing it whenever it is unneeded for correctness and performance. Yet, even in such situations, transient and spurious stalls and irregular data exchanges prevent the systematic removal of handshake logic, thus resulting in an unnecessary resource overhead. In this work, we present a scalable strategy based on linear programming (LP) that eliminates unnecessary and spurious stalls via latency and occupancy balancing; the data exchange periodicity and predictability in the resulting circuits uncover new handshake logic removal opportunities and enable the formation of simple local controllers to replace it. We show that, in cases where dynamism is unneeded, our circuits qualitatively match those produced by standard HLS tools. Otherwise, our strategy allows us to systematically trade off area and performance to exploit various degrees of dynamism depending on the optimization objective. Show more
Permanent link
https://doi.org/10.3929/ethz-b-000670486Publication status
publishedExternal links
Book title
FPGA '24: Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate ArraysPages / Article No.
Publisher
Association for Computing MachineryEvent
Subject
High-level synthesis; dataflow circuits; model checkingFunding
215747 - From Large-Scale Software Applications to Efficient Dataflow Accelerators (SNF)
Notes
Conference lecture held on Mach 5, 2024.More
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ETH Bibliography
yes
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