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A Synergistic Approach to Predictable Compilation and Scheduling on Commodity Multi-Cores
(2020)LCTES '20: The 21st ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded SystemsConference Paper -
Mixed-data-model heterogeneous compilation and OpenMP offloading
(2020)CC 2020: Proceedings of the 29th International Conference on Compiler ConstructionConference Paper -
Taming Data Caches for Predictable Execution on GPU-based SoCs
(2019)Proceedings of the 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)Conference Paper -
Design and Evaluation of SmallFloat SIMD extensions to the RISC-V ISA
(2019)Proceedings of the 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)Conference Paper -
HERO: an Open-Source Research Platform for HW/SW Exploration of Heterogeneous Manycore Systems
(2018)Heterogeneous systems on chip (HeSoCs) co-integrate a high-performance multicore host processor with programmable manycore accelerators (PMCAs) to combine “standard platform” software support (e.g. the Linux OS) with energy-efficient, domain-specific, highly parallel processing capabilities. In this work, we present HERO, a HeSoC platform that tackles this challenge in a novel way HERO’s host processor is an industry-standard ARM ...Conference Paper -
HePREM: Enabling Predictable GPU Execution on Heterogeneous SoC
(2018)2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)Conference Paper -
Scalable and Efficient Virtual Memory Sharing in Heterogeneous SoCs with TLB Prefetching and MMU-Aware DMA Engine
(2018)2018 IEEE 36th International Conference on Computer Design (ICCD)Shared virtual memory (SVM) is key in heterogeneous systems on chip (SoCs), which combine a general-purpose host processor with a many-core accelerator, both for programmability and to avoid data duplication. However, SVM can bring a significant run time overhead when translation lookaside buffer (TLB) entries are missing. Moreover, allowing DMA burst transfers to write SVM traditionally requires buffers to absorb transfers that miss in ...Conference Paper -
A Transprecision Floating-Point Architecture for Energy-Efficient Embedded Computing
(2018)2018 IEEE International Symposium on Circuits and Systems (ISCAS)Conference Paper -
A Transprecision Floating-Point Platform for Ultra-Low Power Computing
(2018)Proceedings of the 2018 Design, Automation & Test in Euro pe Conference & Exhibition (DATE)Conference Paper -
Combining PREM compilation and ILP scheduling for high-performance and predictable MPSoC execution
(2018)Proceedings of the 9th International Workshop on Programming Models and Applications for Multicores and Manycores (PMAM 2018)Conference Paper