Real-time and low latency embedded computer vision hardware based on a combination of FPGA and mobile CPU
dc.contributor.author
Honegger, Dominik
dc.contributor.author
Oleynikova, Helen
dc.contributor.author
Pollefeys, Marc
dc.date.accessioned
2017-06-11T15:15:39Z
dc.date.available
2017-06-11T15:15:39Z
dc.date.issued
2014
dc.identifier.isbn
978-1-4799-6934-0
dc.identifier.isbn
978-1-4799-6935-7
dc.identifier.other
10.1109/IROS.2014.6943263
dc.identifier.uri
http://hdl.handle.net/20.500.11850/95832
dc.language.iso
en
dc.publisher
IEEE
dc.title
Real-time and low latency embedded computer vision hardware based on a combination of FPGA and mobile CPU
dc.type
Conference Paper
ethz.book.title
IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS), 2014 : 14 - 18 Sept. 2014, Chicago, Illinois
ethz.pages.start
4930
ethz.pages.end
4935
ethz.event
2014 IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS)
ethz.event.location
Chicago, IL, USA
ethz.event.date
September 14-18, 2014
ethz.publication.place
Piscataway, NJ
ethz.publication.status
published
ethz.leitzahl
ETH Zürich::00002 - ETH Zürich::00012 - Lehre und Forschung::00007 - Departemente::02150 - Dep. Informatik / Dep. of Computer Science::02659 - Institut für Visual Computing / Institute for Visual Computing::03766 - Pollefeys, Marc / Pollefeys, Marc
ethz.leitzahl.certified
ETH Zürich::00002 - ETH Zürich::00012 - Lehre und Forschung::00007 - Departemente::02150 - Dep. Informatik / Dep. of Computer Science::02659 - Institut für Visual Computing / Institute for Visual Computing::03766 - Pollefeys, Marc / Pollefeys, Marc
ethz.date.deposited
2017-06-11T15:16:14Z
ethz.source
ECIT
ethz.identifier.importid
imp593652c60753a28508
ethz.ecitpid
pub:150241
ethz.eth
yes
ethz.availability
Metadata only
ethz.rosetta.installDate
2017-07-20T14:27:00Z
ethz.rosetta.lastUpdated
2018-11-02T17:40:08Z
ethz.rosetta.versionExported
true
ethz.COinS
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Conference Paper [34963]