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A 72mW 0.03mm2 Inductorless 40Gb/s CDR in 65nm SOI CMOS
(2007)Digest of Technical Papers / IEEE International Solid State Circuits Conference ~ 2007 IEEE International Solid-State Circuits Conference (ISSCC)A quarter-rate CDR circuit is based on a dual-loop approach where sampling phases are generated by a phase-programmable PLL that is controlled by a digital DLL. Implemented in 65nm SOI CMOS, the chip occupies 0.03mm 2 and consumes 1.8mW/Gb/s. Measurements confirm 40Gb/s operation with a BER <10 -12 at a maximum frequency-offset of 400ppm. The phase relation between data and edge samples can be programmed within plusmn0.1 UI.Other Conference Item -
A 16Gb/s Source-Series Terminated Transmitter in 65nm CMOS SOI
(2007)Digest of Technical Papers / IEEE International Solid State Circuits Conference ~ 2007 IEEE International Solid-State Circuits Conference (ISSCC)A half-rate source-series terminated TX, operating at data-rates up to 16Gb/s, targets chip-to-chip on-board interconnects. The TX features a 4-tap FFE, tunable termination, and clock-cleanup circuitry for low duty-cycle distortion, and is capable of driving loads referenced to a variable termination voltage, including Gnd, V DD , and V DD /2. Implemented in 65nm SOI, it occupies an area of 230 times 56mum 2 and draws 57.5mA from a 1V ...Other Conference Item -
A Linear Uplink WCDMA Modulator with 156dBc/Hz Downlink SNR
(2007)Digest of Technical Papers / IEEE International Solid State Circuits Conference ~ 2007 IEEE International Solid-State Circuits Conference (ISSCC)A linearity-boosting technique for upconversion mixers enables a 0.13 μm CMOS WCDMA modulator to achieve -49dBc ACLR and -l56dBc/Hz SNR. The chip consumes 113mW from a 1.2V supply. It is suitable for SAW-filter-free TX implementations. Results show that this technique improves the mixer IIP3 by 6dB.Other Conference Item -
A 0.13μm CMOS EDGE/UMTS/WLAN Tri-Mode ΔΣ ADC with -92dB THD
(2007)Digest of Technical Papers / IEEE International Solid State Circuits Conference ~ 2007 IEEE International Solid-State Circuits Conference (ISSCC)A 2-2 cascaded multi-standard DeltaSigma modulator achieves a OR of 88/79/67dB in EDGE/UMTS/WLAN mode, respectively. With a high linearity of -92dB THD and 34dBm IIP3 for EDGE, this ADC is suitable for wireless applications. Implemented in 0.13 μm CMOS and occupying 0.4mm 2 , the modulator covers 0.1-to-10MHz signal bandwidth with scalable power consumption between 2.9 and 20.5mW from a 1.2V supply.Other Conference Item -
Compact and fully packaged wavelength converter with integrated delay loop for 40 Gbit/s RZ signals
(2000)Optical Fiber Communication ConferenceOther Conference Item -
Effect of a dried and ensiled tanniniferous forage legume (sainfoin) on the nitrogen metabo-lism of growing lambs
(2006)Proceedings of the Society of Nutrition Physiology = Berichte der Gesellschaft für Ernährungsphysiologie ~ 60. Tagung vom 21.-23.03.2006 in GöttingenOther Conference Item -
Triazole Based Chelating Systems for the Tc/Re-Tricarbonyl Core
(2007)Journal of Labelled Compounds and RadiopharmaceuticalsOther Conference Item -
Three-dimensional spectral boundary integral equation analysis of plasmon polaritons enhanced optical nanoantenna
(2008)8th World Congress on Computational Mechanics (WCCM8) ,5th European Congress on Computational Methods in Applied Sciences and Engineering (ECCOMAS 2008)Other Conference Item -
Real-Time Estimation of Current Mean Arterial Blood Pressure Using Intermittent Non-Invasive Measurements and Heart Rate
(2004)Other Conference Item -
New trends and developments in knowledge management and intellectual capital accounting
(2002)Other Conference Item