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GPUguard: Towards supporting a predictable execution model for heterogeneous SoC
(2017)Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017Conference Paper -
HePREM: Enabling Predictable GPU Execution on Heterogeneous SoC
(2018)2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)Conference Paper -
Tightly-coupled hardware support to dynamic parallelism acceleration in embedded shared memory clusters
(2014)2014 Design, Automation & Test in Europe Conference & Exhibition (DATE)Modern designs for embedded systems are increasingly embracing cluster-based architectures, where small sets of cores communicate through tightly-coupled shared memory banks and high-performance interconnections. At the same time, the complexity of modern applications requires new programming abstractions to exploit dynamic and/or irregular parallelism on such platforms. Supporting dynamic parallelism in systems which i) are resource-constrained ...Conference Paper -
A tightly-coupled hardware controller to improve scalability and programmability of shared-memory heterogeneous clusters
(2014)2014 Design, Automation & Test in Europe Conference & Exhibition (DATE)Modern designs for embedded many-core systems increasingly include application-specific units to accelerate key computational kernels with orders-of-magnitude higher execution speed and energy efficiency compared to software counterparts. A promising architectural template is based on heterogeneous clusters, where simple RISC cores and specialized HW units (HWPU) communicate in a tightly-coupled manner via L1 shared memory. Efficiently ...Conference Paper -
HERO: Heterogeneous Embedded Research Platform for Exploring RISC-V Manycore Accelerators on FPGA
(2017)Proceedings of Computer Architecture Research with RISC-V Workshop (CARRV' 17)Heterogeneous embedded systems on chip (HESoCs) co-integrate a standard host processor with programmable manycore accelerators (PMCAs) to combine general-purpose computing with domain-specific, efficient processing capabilities. While leading companies successfully advance their HESoC products, research lags behind due to the challenges of building a prototyping platform that unites an industry-standard host processor with an open ...Conference Paper -
VirtualSoC
(2013)IEEE 27th International Parallel and Distributed Processing Symposium workshops & Phd forum (IPDPSW), 2013 : 20 - 24 May 2013, Cambridge, Boston, Massachusetts, USA ; proceedingsConference Paper -
Scalable and Efficient Virtual Memory Sharing in Heterogeneous SoCs with TLB Prefetching and MMU-Aware DMA Engine
(2018)2018 IEEE 36th International Conference on Computer Design (ICCD)Shared virtual memory (SVM) is key in heterogeneous systems on chip (SoCs), which combine a general-purpose host processor with a many-core accelerator, both for programmability and to avoid data duplication. However, SVM can bring a significant run time overhead when translation lookaside buffer (TLB) entries are missing. Moreover, allowing DMA burst transfers to write SVM traditionally requires buffers to absorb transfers that miss in ...Conference Paper -
An optimized task-based runtime system for resource-constrained parallel accelerators
(2016)Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)Conference Paper -
Speculative synchronization for coherence-free embedded NUMA architectures
(2014)International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS XIV), 2014 : 14 - 17 July 2014, Samos, Greece ; proceedingsConference Paper -
PULP: A Parallel Ultra Low Power platform for next generation IoT Applications
(2016)2015 IEEE Hot Chips 27 Symposium (HCS)Conference Paper