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Self-Sustainability in Nano Unmanned Aerial Vehicles: A Blimp Case Study
(2017)Proceedings of the Computing Frontiers Conference (CF'17)Conference Paper -
Evaluation of Synchronization Protocols for fine-grain HPC sensor data time-stamping and collection
(2016)2016 International Conference on High Performance Computing & Simulation (HPCS 2016)Conference Paper -
Constrained Few-shot Class-incremental Learning
(2022)2022 IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR)Continually learning new classes from fresh data without forgetting previous knowledge of old classes is a very challenging research problem. Moreover, it is imperative that such learning must respect certain memory and computational constraints such as (i) training samples are limited to only a few per class,(ii) the computational cost of learning a novel class remains constant, and (iii) the memory footprint of the model grows at most ...Conference Paper -
ControlPULP: A RISC-V Power Controller for HPC Processors with Parallel Control-Law Computation Acceleration
(2022)Lecture Notes in Computer Science ~ Embedded Computer Systems: Architectures, Modeling, and SimulationConference Paper -
GPUguard: Towards supporting a predictable execution model for heterogeneous SoC
(2017)Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017Conference Paper -
HePREM: Enabling Predictable GPU Execution on Heterogeneous SoC
(2018)2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)Conference Paper -
A 1036 TOp/s/W, 12.2 mW, 2.72 mu J/Inference All Digital TNN Accelerator in 22 nm FDX Technology for TinyML Applications
(2022)2022 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)Tiny Machine Learning (TinyML) applications impose mu J/Inference constraints, with maximum power consumption of a few tens of mW. It is extremely challenging to meet these requirement at a reasonable accuracy level. In this work, we address this challenge with a flexible, fully digital Ternary Neural Network (TNN) accelerator in a RISC-V-based SoC. The design achieves 2.72 mu J/Inference, 12.2 mW, 3200 Inferences/sec at 0.5 V for a ...Conference Paper -
A scan-chain based state retention methodology for IoT processors operating on intermittent energy
(2017)Proceedings of the 2017 Design, Automation & Test in Europe (DATE 2017)Conference Paper -
HERO: Heterogeneous Embedded Research Platform for Exploring RISC-V Manycore Accelerators on FPGA
(2017)Proceedings of Computer Architecture Research with RISC-V Workshop (CARRV' 17)Heterogeneous embedded systems on chip (HESoCs) co-integrate a standard host processor with programmable manycore accelerators (PMCAs) to combine general-purpose computing with domain-specific, efficient processing capabilities. While leading companies successfully advance their HESoC products, research lags behind due to the challenges of building a prototyping platform that unites an industry-standard host processor with an open ...Conference Paper -
Torpor: A Power-Aware HW Scheduler for Energy Harvesting IoT SoCs
(2018)2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)Conference Paper